35 lines
495 B
Verilog
35 lines
495 B
Verilog
module testSAPone;
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wire [7:0] SAP_out;
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wire [11:0] con;
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wire [7:0] bus;
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// wire clk_out, clr_out;
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reg clk, clr_;
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always #5 clk = ~clk;
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SAPone sapone1(
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.SAP_out(SAP_out),
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.con(con),
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.bus(bus),
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// .clk_out(clk_out),
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// .clr_out(clr_out),
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.clk(clk),
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.clr_(clr_)
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);
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// PC pc1(bus[3:0], clk, clr_, cp, ep);
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// MAR mar1(mar, clk, lm_, bus[3:0]);
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initial
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begin
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clk = 0; clr_ = 0;
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#10 clr_ = 1;
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#990 $stop;
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end
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endmodule
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