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OpenFPGA/libs/libopenfpgacapnproto/gen
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tangxifan a1a5f8cfb6 [test] add new test to valid force clock tap mux routing 2024-11-26 17:36:02 -08:00
..
README.gen.md modified test cases & xsd file 2024-10-09 17:21:49 +08:00
unique_blocks.xsd modified test cases & xsd file 2024-10-09 17:21:49 +08:00
unique_blocks_uxsdcxx.capnp [test] add new test to valid force clock tap mux routing 2024-11-26 17:36:02 -08:00

README.gen.md

unique_blocks_uxsdcxx.capnp is generated via uxsdcxx and is checked in to avoid requiring python3 and the uxsdcxx depedencies to build Openfpga.