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adder
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[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
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2021-02-04 20:20:10 -07:00 |
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bram
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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depopulate_crossbar/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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dsp
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[Test] Update test settings for architecture with fracturable DSP blocks
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2021-04-24 15:16:50 -06:00 |
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duplicated_grid_pin/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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fabric_chain
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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flatten_routing/config
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[Test] Deploy default net type option to test case
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2021-02-28 12:20:43 -07:00 |
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fully_connected_output_crossbar/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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io
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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lut_design
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[Test] Update test case to use dedicated eblif file
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2021-02-09 15:51:57 -07:00 |
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mux_design
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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power_gated_design/power_gated_inverter/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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spypad/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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thru_channel
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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untileable/config
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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verilog_netlist_formats
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[Test] Add new test case to test default nettype in different verilog syntax
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2021-02-28 16:16:45 -07:00 |
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