285 lines
14 KiB
C
285 lines
14 KiB
C
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void init_list_include_verilog_netlists(t_spice* spice);
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void init_include_user_defined_verilog_netlists(t_spice spice);
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void dump_include_user_defined_verilog_netlists(FILE* fp,
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t_spice spice);
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void dump_verilog_file_header(FILE* fp,
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char* usage);
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void dump_verilog_preproc(FILE* fp,
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t_syn_verilog_opts fpga_verilog_opts,
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enum e_verilog_tb_type verilog_tb_type);
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void dump_simulation_preproc(FILE* fp,
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t_syn_verilog_opts fpga_verilog_opts,
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enum e_verilog_tb_type verilog_tb_type);
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void dump_verilog_simulation_preproc(char* subckt_dir,
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t_syn_verilog_opts fpga_verilog_opts);
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void dump_verilog_defines_preproc(char* subckt_dir,
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t_syn_verilog_opts fpga_verilog_opts);
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void verilog_include_simulation_defines_file(FILE* fp,
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char* formatted_verilog_dir);
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void verilog_include_defines_preproc_file(FILE* fp,
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char* formatted_verilog_dir);
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FILE* verilog_create_one_subckt_file(char* subckt_dir,
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const char* subckt_name_prefix,
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const char* verilog_subckt_file_name_prefix,
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int grid_x, int grid_y,
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char** verilog_fname);
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void dump_verilog_subckt_header_file(t_llist* subckt_llist_head,
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char* subckt_dir,
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char* header_file_name);
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char determine_verilog_generic_port_split_sign(enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_generic_port(FILE* fp,
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enum e_dump_verilog_port_type dump_port_type,
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char* port_name, int port_lsb, int port_msb);
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void dump_verilog_generic_port_no_repeat(FILE* fp,
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enum e_dump_verilog_port_type dump_port_type,
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char* port_name, int port_lsb, int port_msb);
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char* chomp_verilog_prefix(char* verilog_node_prefix);
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char* format_verilog_node_prefix(char* verilog_node_prefix);
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char* verilog_convert_port_type_to_string(enum e_spice_model_port_type port_type);
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int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp,
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t_spice_model* cur_spice_model,
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boolean dump_port_type,
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boolean recursive,
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boolean require_explicit_port_map);
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int rec_dump_verilog_spice_model_global_ports(FILE* fp,
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t_spice_model* cur_spice_model,
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boolean dump_port_type,
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boolean recursive,
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boolean require_explicit_port_map);
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int dump_verilog_global_ports(FILE* fp, t_llist* head,
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boolean dump_port_type);
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void dump_verilog_mux_sram_one_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_spice_model, int mux_size,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_one_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_mux_sram_one_local_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_spice_model, int mux_size,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_one_local_outport(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_outports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_formal_verification_sram_ports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_one_port(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_local_ports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_reserved_sram_one_port(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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int port_type_index,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb);
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void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_spice_model, int mux_size,
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int sram_lsb, int sram_msb);
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void dump_verilog_reserved_sram_ports(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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int sram_lsb, int sram_msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_mux_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_mux_verilog_model, int mux_size,
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t_spice_model* cur_sram_verilog_model);
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void dump_verilog_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* sram_verilog_model);
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void dump_verilog_scff_config_bus(FILE* fp,
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t_spice_model* mem_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int lsb, int msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_mem_config_bus(FILE* fp, t_spice_model* mem_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int cur_num_sram,
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int num_mem_reserved_conf_bits,
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int num_mem_conf_bits);
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void dump_verilog_cmos_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_mux_config_bus(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model,
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t_sram_orgz_info* cur_sram_orgz_info,
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int mux_size, int cur_num_sram,
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int num_mux_reserved_conf_bits,
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int num_mux_conf_bits);
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void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model,
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char* general_port_prefix, int lsb, int msb,
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enum e_dump_verilog_port_type dump_port_type);
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void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info,
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int lsb, int msb);
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void dump_verilog_toplevel_one_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type,
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int pin_index, int side,
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int x, int y,
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boolean dump_port_type);
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char* generate_verilog_subckt_name(t_spice_model* spice_model,
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char* postfix);
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char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
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t_spice_model* mem_model,
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char* postfix);
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char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
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int mux_size, char* postfix);
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enum e_dump_verilog_port_type
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convert_spice_model_port_type_to_verilog_port_type(enum e_spice_model_port_type spice_model_port_type);
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int dump_verilog_mem_module_one_port_map(FILE* fp,
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t_spice_model* mem_model,
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enum e_spice_model_port_type port_type_to_dump,
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boolean dump_port_type,
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int index, int num_mem, boolean dump_first_comma,
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boolean require_explicit_port_map);
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void dump_verilog_mem_module_port_map(FILE* fp,
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t_spice_model* mem_model,
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boolean dump_port_type,
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int lsb, int num_mem,
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boolean require_explicit_port_map);
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void dump_verilog_mem_sram_submodule(FILE* fp,
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t_sram_orgz_info* cur_sram_orgz_info,
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t_spice_model* cur_verilog_model, int mux_size,
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t_spice_model* cur_sram_verilog_model,
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int lsb, int msb);
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char* gen_verilog_grid_one_pin_name(int x, int y,
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int height, int side, int pin_index,
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boolean for_top_netlist);
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char* gen_verilog_routing_channel_one_pin_name(t_rr_node* chan_rr_node,
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int x, int y, int track_idx,
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enum PORTS pin_direction);
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char* gen_verilog_routing_channel_one_midout_name(t_cb* cur_cb_info,
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int track_idx);
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char* gen_verilog_one_cb_module_name(t_cb* cur_cb_info);
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char* gen_verilog_one_cb_instance_name(t_cb* cur_cb_info);
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char* gen_verilog_one_sb_module_name(t_sb* cur_sb_info);
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char* gen_verilog_one_sb_module_name(size_t rr_sb_id);
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char* gen_verilog_one_sb_instance_name(t_sb* cur_sb_info);
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char* gen_verilog_one_routing_channel_module_name(t_rr_type chan_type,
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int x, int y);
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char* gen_verilog_one_routing_channel_instance_name(t_rr_type chan_type,
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int x, int y);
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char* gen_verilog_one_mux_module_name(t_spice_model* spice_model,
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int mux_size);
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char* gen_verilog_one_grid_instance_name(int grid_x, int grid_y);
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char* gen_verilog_one_grid_module_name(int grid_x, int grid_y);
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char* gen_verilog_one_block_instance_name(int grid_x, int grid_y, int grid_z);
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char* gen_verilog_one_phy_block_instance_name(t_type_ptr cur_type_ptr,
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int block_z);
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char* gen_verilog_one_pb_graph_node_instance_name(t_pb_graph_node* cur_pb_graph_node);
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char* gen_verilog_one_pb_type_pin_name(char* prefix,
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t_port* cur_port, int pin_number);
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char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy(t_pb_graph_pin* cur_pb_graph_pin);
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char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_parent_node(t_pb_graph_pin* cur_pb_graph_pin);
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char* gen_verilog_one_pb_graph_pin_full_name_in_hierarchy_grand_parent_node(t_pb_graph_pin* cur_pb_graph_pin);
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char* gen_verilog_top_module_io_port_prefix(char* global_prefix,
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char* io_port_prefix);
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char* gen_verilog_one_pb_graph_node_full_name_in_hierarchy(t_pb_graph_node* cur_pb_graph_node);
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