217 lines
8.7 KiB
C++
217 lines
8.7 KiB
C++
/********************************************************************
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* This file includes functions to fix up the pb pin mapping results
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* after routing optimization
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_time.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgashell library */
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#include "command_exit_codes.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "pb_type_utils.h"
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#include "lut_utils.h"
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#include "openfpga_lut_truth_table_fixup.h"
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/* Include global variables of VPR */
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#include "globals.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Apply the fix-up to truth table of LUT according to its pin
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* rotation status by packer
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*
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* Note:
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* - pb must represents a LUT pb in the graph and it should be primitive
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*******************************************************************/
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static
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void fix_up_lut_atom_block_truth_table(const AtomContext& atom_ctx,
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t_pb* pb,
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const t_pb_routes& pb_route,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const bool& verbose) {
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t_pb_graph_node* pb_graph_node = pb->pb_graph_node;
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t_pb_type* pb_type = pb->pb_graph_node->pb_type;
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VTR_ASSERT(LUT_CLASS == pb_type->class_type);
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for (int iport = 0; iport < pb_type->num_ports; ++iport) {
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/* We only care about input ports whose pins are equivalent */
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if (IN_PORT != pb_type->ports[iport].type || true == pb_type->ports[iport].is_clock) {
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continue;
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}
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if (pb_type->ports[iport].equivalent == PortEquivalence::NONE) {
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continue;
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}
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/* Reach here, we have to apply a fix-up */
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AtomBlockId atom_blk = atom_ctx.nlist.find_block(pb->name);
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VTR_ASSERT(atom_blk);
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/* Port exists (some LUTs may have no input and hence no port in the atom netlist) */
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AtomPortId atom_port = atom_ctx.nlist.find_atom_port(atom_blk, pb_type->ports[iport].model_port);
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if (!atom_port) {
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continue;
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}
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/* Find the pin rotation status and record it ,
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* Note that some LUT inputs may not be used, we set them to be open by default
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*/
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std::vector<int> rotated_pin_map(pb_type->ports[iport].num_pins, -1);
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for (int ipin = 0; ipin < pb_type->ports[iport].num_pins; ++ipin) {
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int node_index = pb_graph_node->input_pins[iport][ipin].pin_count_in_cluster;
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if (pb_route.count(node_index)) {
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/* The pin is mapped to a net, find the original pin in the atom netlist */
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AtomNetId atom_net = pb_route[node_index].atom_net_id;
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VTR_ASSERT(atom_net);
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for (AtomPinId atom_pin : atom_ctx.nlist.port_pins(atom_port)) {
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AtomNetId atom_pin_net = atom_ctx.nlist.pin_net(atom_pin);
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if (atom_pin_net == atom_net) {
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rotated_pin_map[ipin] = atom_ctx.nlist.pin_port_bit(atom_pin);
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break;
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}
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}
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}
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}
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/* We can apply truth table adaption now
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* For unused inputs : insert dont care
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* For used inputs : find the bit in the truth table rows and move it by the given mapping
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*/
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const AtomNetlist::TruthTable& orig_tt = atom_ctx.nlist.block_truth_table(atom_blk);
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const AtomNetlist::TruthTable& adapt_tt = lut_truth_table_adaption(orig_tt, rotated_pin_map);
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vpr_clustering_annotation.adapt_truth_table(pb, adapt_tt);
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/* Print info is in the verbose mode */
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VTR_LOGV(verbose, "Original truth table\n");
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VTR_LOGV(verbose, "Index: ");
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for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
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if (0 < i) {
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VTR_LOGV(verbose, ",");
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}
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VTR_LOGV(verbose, "%lu", i);
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}
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VTR_LOGV(verbose, "\n");
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for (const std::string& tt_line : truth_table_to_string(orig_tt)) {
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VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
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}
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VTR_LOGV(verbose, "\n");
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VTR_LOGV(verbose, "Pin rotation map: ");
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for (size_t i = 0; i < rotated_pin_map.size(); ++i) {
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if (0 < i) {
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VTR_LOGV(verbose, ",");
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}
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if (-1 == rotated_pin_map[i]) {
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VTR_LOGV(verbose, "open");
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} else {
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VTR_LOGV(verbose, "%lu", rotated_pin_map[i]);
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}
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}
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VTR_LOGV(verbose, "\n");
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VTR_LOGV(verbose, "Adapt truth table\n");
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for (const std::string& tt_line : truth_table_to_string(adapt_tt)) {
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VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
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}
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VTR_LOGV(verbose, "\n");
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}
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}
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/********************************************************************
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* This function recursively visits the pb graph until we reach a
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* LUT pb_type (primitive node in the pb_graph with a class type
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* of LUT_CLASS
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* Once we find a LUT node, we will apply the fix-up
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*******************************************************************/
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static
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void rec_adapt_lut_pb_tt(const AtomContext& atom_ctx,
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t_pb* pb,
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const t_pb_routes& pb_route,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const bool& verbose) {
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t_pb_graph_node* pb_graph_node = pb->pb_graph_node;
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/* If we reach a primitive pb_graph node, we return */
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if (true == is_primitive_pb_type(pb_graph_node->pb_type)) {
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if (LUT_CLASS == pb_graph_node->pb_type->class_type) {
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/* Do fix-up here.
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* Note that LUTs have two modes,
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* For wire modes, we should skip the truth table adaption
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* mode 0 is reserved for wire, see read_xml_arch_file.cpp
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* mode 1 is the regular mode
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*/
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if (1 == pb->mode) {
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fix_up_lut_atom_block_truth_table(atom_ctx, pb->child_pbs[0], pb_route, vpr_clustering_annotation, verbose);
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}
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}
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return;
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}
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/* Recursively visit all the used pbs in the graph */
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t_mode* mapped_mode = &(pb_graph_node->pb_type->modes[pb->mode]);
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for (int ipb = 0; ipb < mapped_mode->num_pb_type_children; ++ipb) {
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/* Each child may exist multiple times in the hierarchy*/
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for (int jpb = 0; jpb < mapped_mode->pb_type_children[ipb].num_pb; ++jpb) {
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/* See if we still have any pb children to walk through */
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if ((pb->child_pbs[ipb] != nullptr) && (pb->child_pbs[ipb][jpb].name != nullptr)) {
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rec_adapt_lut_pb_tt(atom_ctx, &(pb->child_pbs[ipb][jpb]), pb_route, vpr_clustering_annotation, verbose);
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}
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}
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}
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}
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/********************************************************************
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* Main function to fix up truth table for each LUT used in FPGA
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* This function will walk through each clustered block
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*******************************************************************/
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static
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void update_lut_tt_with_post_packing_results(const AtomContext& atom_ctx,
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const ClusteringContext& clustering_ctx,
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VprClusteringAnnotation& vpr_clustering_annotation,
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const bool& verbose) {
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for (auto blk_id : clustering_ctx.clb_nlist.blocks()) {
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rec_adapt_lut_pb_tt(atom_ctx,
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clustering_ctx.clb_nlist.block_pb(blk_id),
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clustering_ctx.clb_nlist.block_pb(blk_id)->pb_route,
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vpr_clustering_annotation, verbose);
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}
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}
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/********************************************************************
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* Top-level function to fix up the lut truth table results after packing is done
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* The problem comes from a mismatch between the packing results and
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* original truth tables in users' BLIF file
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* As LUT inputs are equivalent in nature, the router of packer will try
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* to swap the net mapping among these pins so as to achieve best
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* routing optimization.
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* However, it will cause the original truth table out-of-date when packing is done.
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* This function aims to fix the mess after packing so that the truth table
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* can be synchronized
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*******************************************************************/
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int lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
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const Command& cmd, const CommandContext& cmd_context) {
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vtr::ScopedStartFinishTimer timer("Fix up LUT truth tables after packing optimization");
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CommandOptionId opt_verbose = cmd.option("verbose");
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/* Apply fix-up to each packed block */
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update_lut_tt_with_post_packing_results(g_vpr_ctx.atom(),
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g_vpr_ctx.clustering(),
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openfpga_context.mutable_vpr_clustering_annotation(),
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cmd_context.option_enable(cmd, opt_verbose));
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/* TODO: should identify the error code from internal function execution */
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return CMD_EXEC_SUCCESS;
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}
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} /* end namespace openfpga */
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