106 lines
4.2 KiB
Python
106 lines
4.2 KiB
Python
from string import Template
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import sys
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import os
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import pprint
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import argparse
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import subprocess
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import logging
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from pprint import pprint
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from configparser import ConfigParser
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configure logging system
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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logging.basicConfig(level=logging.INFO, stream=sys.stdout,
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format='%(levelname)s (%(threadName)10s) - %(message)s')
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logger = logging.getLogger('Modelsim_run_log')
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Parse commandline arguments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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parser = argparse.ArgumentParser()
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parser.add_argument('files', nargs='+')
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parser.add_argument('--formality_template', type=str,
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help="Modelsim verification template file")
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parser.add_argument('--run_sim', action="store_true",
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help="Execute generated script in formality")
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args = parser.parse_args()
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# Consider default formality script template
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if not args.formality_template:
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task_script_dir = os.path.dirname(os.path.abspath(__file__))
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args.formality_template = os.path.join(task_script_dir, os.pardir,
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"misc", "formality_template.tcl")
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args.formality_template = os.path.abspath(args.formality_template)
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def main():
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for eachFile in args.files:
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eachFile = os.path.abspath(eachFile)
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pDir = os.path.dirname(eachFile)
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os.chdir(pDir)
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config = ConfigParser()
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config.read(eachFile)
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port_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type port -noninverted" % (
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"/WORK/" + config["BENCHMARK_INFO"]["src_top_module"]
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))
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cell_map = ("set_user_match r:%s/%%s i:/WORK/%%s -type cell -noninverted" % (
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"/WORK/" + config["BENCHMARK_INFO"]["src_top_module"]
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))
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lables = {
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"SOURCE_DESIGN_FILES": config["BENCHMARK_INFO"]["benchmark_netlist"],
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"SOURCE_TOP_MODULE": "/WORK/" + config["BENCHMARK_INFO"]["src_top_module"],
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"IMPL_DESIGN_FILES": " ".join(
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[val for key, val in config["FPGA_INFO"].items()
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if "impl_netlist_" in key]),
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"IMPL_TOP_DIR": "/WORK/" + config["FPGA_INFO"]["impl_top_module"],
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"PORT_MAP_LIST": "\n".join([port_map %
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ele for ele in
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config["PORT_MATCHING"].items()]),
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"REGISTER_MAP_LIST": "\n".join([cell_map %
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ele for ele in
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config["REGISTER_MATCH"].items()]),
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}
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tmpl = Template(open(args.formality_template, encoding='utf-8').read())
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with open(os.path.join(pDir, "Output.tcl"), 'w', encoding='utf-8') as tclout:
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tclout.write(tmpl.substitute(lables))
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if args.run_sim:
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formality_run_string = ["formality", "-file", "Output.tcl"]
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run_command("Formality Run", "formality_run.log", formality_run_string)
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else:
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with open("Output.tcl", 'r', encoding='utf-8') as tclout:
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print(tclout.read())
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def run_command(taskname, logfile, command, exit_if_fail=True):
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os.chdir(os.pardir)
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logger.info("Launching %s " % taskname)
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with open(logfile, 'w+') as output:
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try:
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output.write(" ".join(command)+"\n")
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process = subprocess.run(command,
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check=True,
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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universal_newlines=True)
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output.write(process.stdout)
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if process.returncode:
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logger.error("%s run failed with returncode %d" %
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(taskname, process.returncode))
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except (Exception, subprocess.CalledProcessError) as e:
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logger.exception("failed to execute %s" % taskname)
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return None
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logger.info("%s is written in file %s" % (taskname, logfile))
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return process.stdout
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if __name__ == "__main__":
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main()
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