84 lines
1.2 KiB
Verilog
84 lines
1.2 KiB
Verilog
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// test case generated from IWLS 2005 usb_phy core
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// (triggered a bug in opt_muxtree pass)
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module usb_tx_phy(clk, rst, DataOut_i, TxValid_i, hold_reg);
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input clk;
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input rst;
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input DataOut_i;
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input TxValid_i;
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output reg hold_reg;
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reg state, next_state;
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reg ld_sop_d;
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reg ld_data_d;
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always @(posedge clk)
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if(ld_sop_d)
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hold_reg <= 0;
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else
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hold_reg <= DataOut_i;
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always @(posedge clk)
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if(!rst) state <= 0;
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else state <= next_state;
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always @(state or TxValid_i)
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begin
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next_state = state;
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ld_sop_d = 1'b0;
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ld_data_d = 1'b0;
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case(state) // synopsys full_case parallel_case
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0:
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if(TxValid_i)
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begin
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ld_sop_d = 1'b1;
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next_state = 1;
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end
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1:
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if(TxValid_i)
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begin
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ld_data_d = 1'b1;
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next_state = 0;
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end
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endcase
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end
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endmodule
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// test case inspired by softusb_navre code:
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// default not as last case
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module default_cases(a, y);
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input [2:0] a;
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output reg [3:0] y;
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always @* begin
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case (a)
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3'b000, 3'b111: y <= 0;
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default: y <= 4;
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3'b001: y <= 1;
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3'b010: y <= 2;
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3'b100: y <= 3;
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endcase
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end
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endmodule
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// test case for muxtree with select on leaves
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module select_leaves(input R, C, D, output reg Q);
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always @(posedge C)
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if (!R)
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Q <= R;
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else
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Q <= Q ? Q : D ? D : Q;
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endmodule
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