OpenFPGA/openfpga
tangxifan e4d7192e50 [core] fixed a bug where subtile was used for clock network tap name 2024-08-09 16:16:05 -07:00
..
src [core] fixed a bug where subtile was used for clock network tap name 2024-08-09 16:16:05 -07:00
CMakeLists.txt [lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules 2023-09-15 13:51:14 -07:00