OpenFPGA/openfpga_flow/arch/vpr_only_templates
tangxifan 600a48edc7 add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
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k6_N10_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_N10_tileable_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_adder_chain_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_adder_chain_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_chain_40nm.xml add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml add test case of BRAM to Travis CI 2020-04-12 14:27:05 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00
k6_frac_N10_tileable_adder_register_chain_40nm.xml add more test vpr architecture to regression tests 2020-04-12 12:49:16 -06:00
k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml add more test vpr architecture to regression tests 2020-04-12 12:49:16 -06:00
k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml Added XML and benchmarks for testing 2020-04-06 00:32:06 -06:00