tangxifan af1628abfe use bus port for primitives in Verilog generator		2019-06-13 16:26:58 -06:00
..
base	fix bugs in CMakeList on enable/disable VPR Graphics	2019-06-12 22:48:00 -06:00
bitstream	use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB	2019-06-10 12:50:10 -06:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
router	Merge remote-tracking branch 'origin' into tileable_sb	2019-06-05 13:31:49 -06:00
shell	Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb	2019-05-13 14:45:57 -06:00
spice	fix a bug for iopad SPICE generation	2019-06-11 11:43:56 -06:00
verilog	use bus port for primitives in Verilog generator	2019-06-13 16:26:58 -06:00