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OpenFPGA/vpr7_x2p/vpr/SRC
History
tangxifan af1628abfe use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
..
base fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
device/rr_graph fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00
fpga_x2p use bus port for primitives in Verilog generator 2019-06-13 16:26:58 -06:00
mrfpga cleaned unused variables 2019-05-13 14:45:02 -06:00
pack cleaned unused variables 2019-05-13 14:45:02 -06:00
place cleaned unused variables 2019-05-13 14:45:02 -06:00
power rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
route start developing tileable_rr_graph_builder 2019-06-11 16:49:10 -06:00
timing rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
util cleaned unused variables 2019-05-13 14:45:02 -06:00
ctags_vpr_src.sh Correction of the SDC to remove global clocks 2019-05-30 15:04:21 -06:00
main.c cleaned unused variables 2019-05-13 14:45:02 -06:00
shell_main.c Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00