tangxifan 5f61cd8876 Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb ... Conflicts: vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c		2019-06-13 16:32:39 -06:00
..
ARCH	Update spice path in architecture	2019-05-29 10:08:58 -06:00
Circuits	Add missing Verilog source, Archictecture folder and Testbenches correction	2019-05-13 16:41:35 -06:00
SRC	use bus port for primitives in Verilog generator	2019-06-13 16:26:58 -06:00
SpiceNetlists	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
VerilogNetlists	fix path in regression test! TODO: must keep a duplicated copy for template.xml	2019-06-07 23:31:42 -06:00
CMakeLists.txt	fixed a bug in Verilog generator supporting SRAM5T	2019-06-13 14:42:39 -06:00
go_fpga_spice.sh	Update VPR7 X2P with new engine	2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh	rename rr_switch_block to rr_gsb, a generic block	2019-06-06 17:41:01 -06:00
regression_verilog.sh	Add a script to create a new file with correct path rather than overwrite the existing	2019-06-11 14:28:58 -06:00