205 lines
7.6 KiB
C++
205 lines
7.6 KiB
C++
#ifndef FABRIC_KEY_H
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#define FABRIC_KEY_H
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/********************************************************************
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* This file include the declaration of fabric key
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*******************************************************************/
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#include <array>
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#include <map>
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#include <string>
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/* Headers from vtrutil library */
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#include "vtr_geometry.h"
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#include "vtr_vector.h"
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/* Headers from openfpgautil library */
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#include "fabric_key_fwd.h"
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#include "openfpga_port.h"
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/********************************************************************
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* A data structure to describe a secure key for fabric organization
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* A fabric may consist of multiple regions
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* Each region contains a number of keys
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*
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* Note that:
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* - each key can only be defined in one unique region
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*
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* Typical usage:
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* --------------
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* // Create an empty fabric key
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* FabricKey fabric_key;
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* // Create a region
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* FabricRegionId region = fabric_key.create_region();
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* // Add a key with name and value
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* FabricKeyId key = fabric_key.create_key(key_name, key_value);
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* // Affilate a key to a region
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* fabric_key.add_key_to_region(region, key);
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*
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*******************************************************************/
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class FabricKey {
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public: /* Types */
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typedef vtr::vector<FabricKeyId, FabricKeyId>::const_iterator
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fabric_key_iterator;
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typedef vtr::vector<FabricRegionId, FabricRegionId>::const_iterator
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fabric_region_iterator;
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typedef vtr::vector<FabricBitLineBankId, FabricBitLineBankId>::const_iterator
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fabric_bit_line_bank_iterator;
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typedef vtr::vector<FabricWordLineBankId,
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FabricWordLineBankId>::const_iterator
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fabric_word_line_bank_iterator;
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/* Create range */
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typedef vtr::Range<fabric_region_iterator> fabric_region_range;
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typedef vtr::Range<fabric_key_iterator> fabric_key_range;
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typedef vtr::Range<fabric_bit_line_bank_iterator> fabric_bit_line_bank_range;
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typedef vtr::Range<fabric_word_line_bank_iterator>
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fabric_word_line_bank_range;
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public: /* Constructors */
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FabricKey();
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public: /* Accessors: aggregates */
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fabric_key_range keys() const;
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fabric_region_range regions() const;
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fabric_bit_line_bank_range bl_banks(const FabricRegionId& region_id) const;
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fabric_word_line_bank_range wl_banks(const FabricRegionId& region_id) const;
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public: /* Public Accessors: Basic data query */
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/* Access all the keys of a region */
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std::vector<FabricKeyId> region_keys(const FabricRegionId& region_id) const;
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/* Access the name of a key */
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std::string key_name(const FabricKeyId& key_id) const;
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/* Access the value of a key */
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size_t key_value(const FabricKeyId& key_id) const;
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/* Access the alias of a key */
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std::string key_alias(const FabricKeyId& key_id) const;
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/* Access the coordinate of a key */
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vtr::Point<int> key_coordinate(const FabricKeyId& key_id) const;
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/* Check if there are any keys */
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bool empty() const;
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/* Return a list of data ports which will be driven by a BL shift register
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* bank */
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std::vector<openfpga::BasicPort> bl_bank_data_ports(
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const FabricRegionId& region_id, const FabricBitLineBankId& bank_id) const;
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/* Return a list of data ports which will be driven by a WL shift register
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* bank */
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std::vector<openfpga::BasicPort> wl_bank_data_ports(
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const FabricRegionId& region_id, const FabricWordLineBankId& bank_id) const;
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public: /* Public Mutators: model-related */
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/* Reserve a number of regions to be memory efficent */
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void reserve_regions(const size_t& num_regions);
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/* Create a new region and add it to the library, return an id */
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FabricRegionId create_region();
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/* Reserve the memory space for keys under a region, to be memory efficient */
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void reserve_region_keys(const FabricRegionId& region_id,
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const size_t& num_keys);
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/* Add a key to a region */
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void add_key_to_region(const FabricRegionId& region_id,
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const FabricKeyId& key_id);
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/* Reserve a number of keys to be memory efficent */
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void reserve_keys(const size_t& num_keys);
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/* Create a new key and add it to the library, return an id */
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FabricKeyId create_key();
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/* Configure attributes of a key */
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void set_key_name(const FabricKeyId& key_id, const std::string& name);
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void set_key_value(const FabricKeyId& key_id, const size_t& value);
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void set_key_alias(const FabricKeyId& key_id, const std::string& alias);
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void set_key_coordinate(const FabricKeyId& key_id,
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const vtr::Point<int>& coord);
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/* Reserve a number of banks to be memory efficent */
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void reserve_bl_shift_register_banks(const FabricRegionId& region_id,
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const size_t& num_banks);
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void reserve_wl_shift_register_banks(const FabricRegionId& region_id,
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const size_t& num_banks);
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/* Create a new shift register bank for BLs and return an id */
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FabricBitLineBankId create_bl_shift_register_bank(
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const FabricRegionId& region_id);
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/* Add a data port to a given BL shift register bank */
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void add_data_port_to_bl_shift_register_bank(
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const FabricRegionId& region_id, const FabricBitLineBankId& bank_id,
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const openfpga::BasicPort& data_port);
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/* Create a new shift register bank for WLs and return an id */
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FabricWordLineBankId create_wl_shift_register_bank(
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const FabricRegionId& region_id);
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/* Add a data port to a given WL shift register bank */
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void add_data_port_to_wl_shift_register_bank(
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const FabricRegionId& region_id, const FabricWordLineBankId& bank_id,
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const openfpga::BasicPort& data_port);
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public: /* Public invalidators/validators */
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bool valid_region_id(const FabricRegionId& region_id) const;
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bool valid_key_id(const FabricKeyId& key_id) const;
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/* Identify if key coordinate is acceptable to fabric key convention */
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bool valid_key_coordinate(const vtr::Point<int>& coord) const;
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bool valid_bl_bank_id(const FabricRegionId& region_id,
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const FabricBitLineBankId& bank_id) const;
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bool valid_wl_bank_id(const FabricRegionId& region_id,
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const FabricWordLineBankId& bank_id) const;
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private: /* Internal data */
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/* Unique ids for each region */
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vtr::vector<FabricRegionId, FabricRegionId> region_ids_;
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/* Key ids for each region */
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vtr::vector<FabricRegionId, std::vector<FabricKeyId>> region_key_ids_;
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/* Unique ids for each key */
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vtr::vector<FabricKeyId, FabricKeyId> key_ids_;
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/* Names for each key */
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vtr::vector<FabricKeyId, std::string> key_names_;
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/* Values for each key */
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vtr::vector<FabricKeyId, size_t> key_values_;
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/* Values for each key */
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vtr::vector<FabricKeyId, vtr::Point<int>> key_coordinates_;
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/* Region for each key */
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vtr::vector<FabricKeyId, FabricRegionId> key_regions_;
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/* Optional alias for each key, with which a key can also be represented */
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vtr::vector<FabricKeyId, std::string> key_alias_;
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/* Unique ids for each BL shift register bank */
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vtr::vector<FabricRegionId,
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vtr::vector<FabricBitLineBankId, FabricBitLineBankId>>
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bl_bank_ids_;
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/* Data ports to be connected to each BL shift register bank */
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vtr::vector<FabricRegionId, vtr::vector<FabricBitLineBankId,
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std::vector<openfpga::BasicPort>>>
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bl_bank_data_ports_;
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/* Unique ids for each WL shift register bank */
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vtr::vector<FabricRegionId,
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vtr::vector<FabricWordLineBankId, FabricWordLineBankId>>
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wl_bank_ids_;
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/* Data ports to be connected to each WL shift register bank */
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vtr::vector<FabricRegionId, vtr::vector<FabricWordLineBankId,
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std::vector<openfpga::BasicPort>>>
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wl_bank_data_ports_;
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};
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#endif
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