9 lines
477 B
Plaintext
9 lines
477 B
Plaintext
[GENERAL CONFIGURATION]
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task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks
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circuits_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/Verilog/MCNC/
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archs_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/arch
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misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc
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script_default=${PATH:OPENFPGA_PATH}/fpga_flow/scripts/fpga_flow.pl
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csv_rpt_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/csv_rpt/
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verilog_output_path=${PATH:OPENFPGA_PATH}/openfpga_flow/verilog_op/
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temp_run_dir=${PATH:OPENFPGA_PATH} |