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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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5c646f5de7
OpenFPGA
/
vpr7_x2p
/
vpr
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tangxifan
5c646f5de7
fix bugs in routing identification
2019-05-09 21:40:06 -06:00
..
SRC
fix bugs in routing identification
2019-05-09 21:40:06 -06:00
SpiceNetlists
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
VerilogNetlists
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
CMakeLists.txt
Add latest abc and update ace dependence
2019-05-03 18:56:03 -06:00
Makefile
fixed bugs in CMakeLists.txt and Makefile
2019-05-03 23:03:04 -06:00
go_fpga_spice.sh
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
go_fpga_verilog.sh
finish the identification on mirror switch and connection blocks
2019-05-09 21:31:39 -06:00