50 lines
2.4 KiB
Plaintext
50 lines
2.4 KiB
Plaintext
# Run VPR for the 'and' design
|
|
#--write_rr_graph example_rr_graph.xml
|
|
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
|
|
|
|
# Read OpenFPGA architecture definition
|
|
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
|
|
|
# Read OpenFPGA simulation settings
|
|
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
|
|
|
# Annotate the OpenFPGA architecture to VPR data base
|
|
# to debug use --verbose options
|
|
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
|
|
|
# Call a file to run a few commands
|
|
source --command_stream ${OPENFPGA_EXTERNAL_SHELL_SCRIPT_DIR}/external_file_for_source_example_script.openfpga --from_file --batch_mode
|
|
|
|
# Write fabric-dependent bitstream
|
|
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
|
|
|
|
# Write the Verilog netlist for FPGA fabric
|
|
# - Enable the use of explicit port mapping in Verilog netlist
|
|
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
|
|
|
|
# Write the Verilog testbench for FPGA fabric
|
|
# - We suggest the use of same output directory as fabric Verilog netlists
|
|
# - Must specify the reference benchmark file if you want to output any testbenches
|
|
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
|
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
|
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
|
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
|
|
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping
|
|
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping
|
|
|
|
# Write the SDC files for PnR backend
|
|
# - Turn on every options here
|
|
write_pnr_sdc --file ./SDC
|
|
|
|
# Write SDC to disable timing for configure ports
|
|
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
|
|
|
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
|
write_analysis_sdc --file ./SDC_analysis
|
|
|
|
# Finish and exit OpenFPGA
|
|
exit
|
|
|
|
# Note :
|
|
# To run verification at the end of the flow maintain source in ./SRC directory
|