316 lines
13 KiB
C++
316 lines
13 KiB
C++
#ifndef OPENFPGA_SDC_COMMAND_TEMPLATE_H
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#define OPENFPGA_SDC_COMMAND_TEMPLATE_H
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/********************************************************************
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* Add commands to the OpenFPGA shell interface,
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* in purpose of generate SDC files
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* - write_pnr_sdc : generate SDC to constrain the back-end flow for FPGA fabric
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* - write_analysis_sdc: TODO: generate SDC based on users' implementations
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*******************************************************************/
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#include "openfpga_sdc_template.h"
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#include "shell.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_pnr_sdc_command_template(
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openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
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Command shell_cmd("write_pnr_sdc");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "Specify the output directory for SDC files");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--flatten_name' */
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shell_cmd.add_option("flatten_names", false,
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"Use flatten names (no wildcards) in SDC files");
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/* Add an option '--hierarchical' */
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shell_cmd.add_option(
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"hierarchical", false,
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"Output SDC files hierachically (without full path in hierarchy)");
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/* Add an option '--output_hierarchy' */
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shell_cmd.add_option(
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"output_hierarchy", false,
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"Output hierachy of Multiple-Instance-Blocks (MIBs) to plain text file. "
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"This is applied to constrain timing for grid, SBs and CBs");
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/* Add an option '--time_unit' */
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CommandOptionId time_unit_opt = shell_cmd.add_option(
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"time_unit", false,
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"Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s");
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shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
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/* Add an option '--constrain_global_port' */
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shell_cmd.add_option("constrain_global_port", false,
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"Constrain all the global ports of FPGA fabric");
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/* Add an option '--constrain_non_clock_global_port' */
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shell_cmd.add_option(
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"constrain_non_clock_global_port", false,
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"Constrain all the non-clock global ports as clock ports of FPGA fabric");
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/* Add an option '--constrain_grid' */
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shell_cmd.add_option("constrain_grid", false,
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"Constrain all the grids of FPGA fabric");
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/* Add an option '--constrain_sb' */
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shell_cmd.add_option("constrain_sb", false,
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"Constrain all the switch blocks of FPGA fabric");
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/* Add an option '--constrain_cb' */
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shell_cmd.add_option("constrain_cb", false,
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"Constrain all the connection blocks of FPGA fabric");
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/* Add an option '--constrain_configurable_memory_outputs' */
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shell_cmd.add_option(
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"constrain_configurable_memory_outputs", false,
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"Constrain all the outputs of configurable memories of FPGA fabric");
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/* Add an option '--constrain_routing_multiplexer_outputs' */
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shell_cmd.add_option(
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"constrain_routing_multiplexer_outputs", false,
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"Constrain all the outputs of routing multiplexer of FPGA fabric");
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/* Add an option '--constrain_switch_block_outputs' */
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shell_cmd.add_option(
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"constrain_switch_block_outputs", false,
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"Constrain all the outputs of switch blocks of FPGA fabric");
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/* Add an option '--constrain_zero_delay_paths' */
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shell_cmd.add_option("constrain_zero_delay_paths", false,
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"Constrain zero-delay paths in FPGA fabric");
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/* Add an option '--no_time_stamp' */
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shell_cmd.add_option("no_time_stamp", false,
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"Do not print time stamp in output files");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd,
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"generate SDC files to constrain the backend flow for FPGA fabric", hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(shell_cmd_id,
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write_pnr_sdc_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC for configuration
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*chain
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_configuration_chain_sdc_command_template(
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openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
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Command shell_cmd("write_configuration_chain_sdc");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "Specify the SDC file to constrain configuration chain");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--time_unit' */
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CommandOptionId time_unit_opt = shell_cmd.add_option(
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"time_unit", false,
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"Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|k|M]s");
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shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
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/* Add an option '--min_delay' */
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CommandOptionId min_dly_opt = shell_cmd.add_option(
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"min_delay", false, "Specify the minimum delay to be used.");
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shell_cmd.set_option_require_value(min_dly_opt, openfpga::OPT_STRING);
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/* Add an option '--max_delay' */
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CommandOptionId max_dly_opt = shell_cmd.add_option(
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"max_delay", false, "Specify the maximum delay to be used.");
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shell_cmd.set_option_require_value(max_dly_opt, openfpga::OPT_STRING);
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/* Add an option '--no_time_stamp' */
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shell_cmd.add_option("no_time_stamp", false,
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"Do not print time stamp in output files");
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/* Add command 'write_configuration_chain_sdc' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd,
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"generate SDC files to constrain the configuration chain for FPGA fabric",
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hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(
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shell_cmd_id, write_configuration_chain_sdc_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC for configure ports
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_sdc_disable_timing_configure_ports_command_template(
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openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
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Command shell_cmd("write_sdc_disable_timing_configure_ports");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt =
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shell_cmd.add_option("file", true, "Specify the output directory");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--flatten_name' */
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shell_cmd.add_option("flatten_names", false,
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"Use flatten names (no wildcards) in SDC files");
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/* Add an option '--no_time_stamp' */
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shell_cmd.add_option("no_time_stamp", false,
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"Do not print time stamp in output files");
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose outputs");
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/* Add command 'write_configuration_chain_sdc' to the Shell */
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ShellCommandId shell_cmd_id =
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shell.add_command(shell_cmd,
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"generate SDC files to disable timing for configure "
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"ports across FPGA fabric",
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hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(
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shell_cmd_id, write_sdc_disable_timing_configure_ports_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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/********************************************************************
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* - Add a command to Shell environment: generate PnR SDC
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* - Add associated options
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* - Add command dependency
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*******************************************************************/
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template <class T>
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ShellCommandId add_write_analysis_sdc_command_template(
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openfpga::Shell<T>& shell, const ShellCommandClassId& cmd_class_id,
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const std::vector<ShellCommandId>& dependent_cmds, const bool& hidden) {
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Command shell_cmd("write_analysis_sdc");
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/* Add an option '--file' in short '-f'*/
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CommandOptionId output_opt = shell_cmd.add_option(
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"file", true, "Specify the output directory for SDC files");
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shell_cmd.set_option_short_name(output_opt, "f");
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shell_cmd.set_option_require_value(output_opt, openfpga::OPT_STRING);
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/* Add an option '--verbose' */
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shell_cmd.add_option("verbose", false, "Enable verbose output");
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/* Add an option '--flatten_name' */
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shell_cmd.add_option("flatten_names", false,
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"Use flatten names (no wildcards) in SDC files");
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/* Add an option '--time_unit' */
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CommandOptionId time_unit_opt = shell_cmd.add_option(
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"time_unit", false,
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"Specify the time unit in SDC files. Acceptable is [a|f|p|n|u|m|kM]s");
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shell_cmd.set_option_require_value(time_unit_opt, openfpga::OPT_STRING);
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/* Add an option '--no_time_stamp' */
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shell_cmd.add_option("no_time_stamp", false,
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"Do not print time stamp in output files");
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/* Add command 'write_fabric_verilog' to the Shell */
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ShellCommandId shell_cmd_id =
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shell.add_command(shell_cmd,
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"generate SDC files for timing analysis a PnRed FPGA "
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"fabric mapped by a benchmark",
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hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_const_execute_function(shell_cmd_id,
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write_analysis_sdc_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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return shell_cmd_id;
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}
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template <class T>
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void add_openfpga_sdc_command_templates(openfpga::Shell<T>& shell,
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const bool& hidden = false) {
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/* Get the unique id of 'build_fabric' command which is to be used in creating
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* the dependency graph */
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const ShellCommandId& build_fabric_id =
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shell.command(std::string("build_fabric"));
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/* Add a new class of commands */
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ShellCommandClassId openfpga_sdc_cmd_class =
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shell.add_command_class("FPGA-SDC");
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/********************************
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* Command 'write_pnr_sdc'
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*/
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/* The 'write_pnr_sdc' command should NOT be executed before 'build_fabric' */
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std::vector<ShellCommandId> pnr_sdc_cmd_dependency;
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pnr_sdc_cmd_dependency.push_back(build_fabric_id);
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add_write_pnr_sdc_command_template<T>(shell, openfpga_sdc_cmd_class,
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pnr_sdc_cmd_dependency, hidden);
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/********************************
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* Command 'write_configuration_chain_sdc'
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*/
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/* The 'write_configuration_chain_sdc' command should NOT be executed before
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* 'build_fabric' */
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std::vector<ShellCommandId> cc_sdc_cmd_dependency;
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cc_sdc_cmd_dependency.push_back(build_fabric_id);
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add_write_configuration_chain_sdc_command_template<T>(
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shell, openfpga_sdc_cmd_class, cc_sdc_cmd_dependency, hidden);
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/********************************
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* Command 'write_sdc_disable_timing_configure_ports'
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*/
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/* The 'write_sdc_disable_timing_configure_ports' command should NOT be
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* executed before 'build_fabric' */
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std::vector<ShellCommandId> config_port_sdc_cmd_dependency;
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config_port_sdc_cmd_dependency.push_back(build_fabric_id);
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add_write_sdc_disable_timing_configure_ports_command_template<T>(
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shell, openfpga_sdc_cmd_class, config_port_sdc_cmd_dependency, hidden);
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/********************************
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* Command 'write_analysis_sdc'
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*/
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/* The 'write_analysis_sdc' command should NOT be executed before
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* 'build_fabric' */
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std::vector<ShellCommandId> analysis_sdc_cmd_dependency;
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analysis_sdc_cmd_dependency.push_back(build_fabric_id);
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add_write_analysis_sdc_command_template<T>(
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shell, openfpga_sdc_cmd_class, analysis_sdc_cmd_dependency, hidden);
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}
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} /* end namespace openfpga */
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#endif
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