67 lines
1.4 KiB
Bash
Executable File
67 lines
1.4 KiB
Bash
Executable File
#!/bin/bash
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source .travis/common.sh
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set -e
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$SPACER
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start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
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if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
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#make
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mkdir build
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cd build
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cmake ..
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make -j2
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else
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# For linux, we enable full package compilation
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#make
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mkdir build
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cd build
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cmake ..
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make -j2
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fi
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# Begining of Verilog verification
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# Set variables
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set benchmark = test_modes
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set include_netlists = _include_netlists.v
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set compiled_file = compiled_$benchmark
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set tb_formal_postfix = _top_formal_verification_random_tb
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set verilog_output_dirname = ${benchmark}_Verilog
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set log_file = ${benchmark}_sim.log
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# Move to vpr folder
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cd vpr7_x2p/vpr
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# Remove former log file
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rm $log_file
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rm $compiled_file
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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source .regression_verilog.sh
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iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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vvp $compiled_file -j 16 >> $log_file
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set result = `grep "Succeed" $log_file`
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if ("$result" != "")then
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echo "Verification succeed"
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cd -
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exit 0
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else
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set result = `grep "Failed" $log_file`
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if ("$result" != "")then
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echo "Verification failed"
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cd -
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exit 1
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else
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echo "Unexpected error, Verification didn't run"
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cd -
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exit 2
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fi
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fi
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# End of Verilog verification
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end_section "OpenFPGA.build"
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$SPACER
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