119 lines
4.4 KiB
C++
119 lines
4.4 KiB
C++
#ifndef IO_PIN_TABLE_H
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#define IO_PIN_TABLE_H
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/********************************************************************
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* This file include the declaration of pin constraints
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*******************************************************************/
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#include <array>
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#include <map>
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#include <string>
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/* Headers from vtrutil library */
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#include "vtr_geometry.h"
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#include "vtr_vector.h"
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/* Headers from libarchfpga library */
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#include "physical_types.h"
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/* Headers from openfpgautil library */
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#include "io_pin_table_fwd.h"
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#include "openfpga_port.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* A data structure to describe the I/O pin table for FPGA fabrics
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* This data structure may include a number of I/O pins
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* each of which contains the following information
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* - side: the side which this I/O locates on FPGA perimeter
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* - external_pin_name: the name of the external I/O pin (typically on a
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*packaged chip), which is exposed to end-users
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* - internal_pin_name: the name of the internal I/O pin (typically inside the
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*chip but on an FPGA fabric), which is defined in FPGA netlists
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* - direction: the direction of the internal pin, can be input, output or inout
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*
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* The following figure illustrates the relationship between external and
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*internal pins. FPGA Chip
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* +----------------------------------------
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* | FPGA fabric
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* | +----------------------
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* | +----- + |
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* CHIP_IO_TOP --->|--->| I/O |--->| FPGA_IN[0]
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* (External pin) | | Ctrl | | (internal pin as input)
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* | | |<---| FPGA_OUT[1]
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* | +------+ | (internal pin as output)
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*
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* Typical usage:
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* --------------
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* // Create an object
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* IoPinTable io_pin_table;
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* // Add a pin
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* openfpga::BasicPort ext_pin_info("CHIP_IO_TOP", 1);
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* openfpga::BasicPort int_pin_info("FPGA_IN", 1, 1);
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* IoPinTableId pin_id = io_pin_table.create_io_pin(int_pin_info,
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*ext_pin_info, TOP, INPUT);
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*
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*******************************************************************/
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class IoPinTable {
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public: /* Types */
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typedef vtr::vector<IoPinTableId, IoPinTableId>::const_iterator
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io_pin_table_iterator;
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/* Create range */
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typedef vtr::Range<io_pin_table_iterator> io_pin_table_range;
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/* Logic value */
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enum e_io_direction { INPUT, OUTPUT, NUM_IO_DIRECTIONS };
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public: /* Constructors */
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IoPinTable();
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public: /* Accessors: aggregates */
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/* Walk through the internal pins. We do not walk through external pins
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* because they are not unique in the table. An external pin may be accessible
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* by two internal pins
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*/
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io_pin_table_range pins() const;
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public: /* Public Accessors: Basic data query */
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/* Get the basic information for a pin */
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BasicPort internal_pin(const IoPinTableId& pin_id) const;
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BasicPort external_pin(const IoPinTableId& pin_id) const;
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e_side pin_side(const IoPinTableId& pin_id) const;
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e_io_direction pin_direction(const IoPinTableId& pin_id) const;
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/* Given an external pin, find all the internal pin that is mapped */
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std::vector<IoPinTableId> find_internal_pin(
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const BasicPort& ext_pin, const e_io_direction& pin_direction) const;
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/* Check if there are any pins */
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bool empty() const;
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public: /* Public Mutators */
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/* Reserve to be memory efficent */
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void reserve_pins(const size_t& num_pins);
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/* Add a pin to storage */
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IoPinTableId create_pin();
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/* Set pin attributes */
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void set_internal_pin(const IoPinTableId& pin_id, const BasicPort& pin);
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void set_external_pin(const IoPinTableId& pin_id, const BasicPort& pin);
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void set_pin_side(const IoPinTableId& pin_id, const e_side& side);
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void set_pin_direction(const IoPinTableId& pin_id,
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const e_io_direction& direction);
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public: /* Public invalidators/validators */
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/* Show if the pin id is a valid for data queries */
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bool valid_pin_id(const IoPinTableId& pin_id) const;
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private: /* Internal data */
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/* Unique ids for each design constraint */
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vtr::vector<IoPinTableId, IoPinTableId> pin_ids_;
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/* Pin information*/
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vtr::vector<IoPinTableId, BasicPort> internal_pins_;
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vtr::vector<IoPinTableId, BasicPort> external_pins_;
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vtr::vector<IoPinTableId, e_side> pin_sides_;
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vtr::vector<IoPinTableId, e_io_direction> pin_directions_;
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};
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} /* end namespace openfpga */
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#endif
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