13 lines
358 B
Verilog
13 lines
358 B
Verilog
module demo(input clk, reset, ctrl);
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localparam NBITS = 10;
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reg [NBITS-1:0] counter;
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initial counter[NBITS-2] = 0;
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initial counter[0] = 1;
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always @(posedge clk) begin
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counter <= reset ? 1 : ctrl ? counter + 1 : counter - 1;
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assume(counter != 0);
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assume(counter != 1 << (NBITS-1));
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assert(counter != (1 << NBITS)-1);
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end
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endmodule
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