260 lines
6.8 KiB
Verilog
260 lines
6.8 KiB
Verilog
module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s == 0) o <= i[0*W+:W];
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else if (s == 1) o <= i[1*W+:W];
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else if (s == 2) o <= i[2*W+:W];
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else if (s == 3) o <= i[3*W+:W];
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 2) o <= i[2*W+:W];
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if (s == 3) o <= i[3*W+:W];
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if (s == 4) o <= i[4*W+:W];
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end
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endmodule
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module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s != 0)
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if (s != 1)
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if (s != 2)
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if (s != 3)
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if (s != 4) o <= i[4*W+:W];
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else o <= i[0*W+:W];
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else o <= i[3*W+:W];
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else o <= i[2*W+:W];
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else o <= i[1*W+:W];
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 2) o[W-2:0] <= i[2*W+:W-1];
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if (s == 3) o <= i[3*W+:W];
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if (s == 4) o <= i[4*W+:W];
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end
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endmodule
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module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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if (s == 0) o <= i[0*W+:W];
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// else if (s == 1) o <= i[1*W+:W];
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// else if (s == 2) o <= i[2*W+:W];
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else if (s == 3) o <= i[3*W+:W];
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else o <= {W{1'bx}};
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end
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endmodule
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module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 3) o <= i[3*W+:W];
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if (s == 2) o <= i[2*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 4) o <= i[4*W+:W];
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if (s == 0) o <= i[0*W+:W];
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end
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endmodule
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module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s == 0) o <= i[0*W+:W];
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else if (s == 1) o <= i[1*W+:W];
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else if (s == 2) o <= i[2*W+:W];
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else if (s == 3) o <= i[3*W+:W];
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else if (s == 0) o <= {W{1'b0}};
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else o <= {W{1'bx}};
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endmodule
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module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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if (s == 0) o <= i[0*W+:W];
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if (s == 1) o <= i[1*W+:W];
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if (s == 2) o <= i[2*W+:W];
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if (s == 3) o <= i[3*W+:W];
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if (s == 4) o <= i[4*W+:W];
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if (s == 0) o <= i[2*W+:W];
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end
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endmodule
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module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @* begin
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o <= {W{1'bx}};
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case (s)
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0: o <= i[0*W+:W];
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default:
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case (s)
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1: o <= i[1*W+:W];
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2: o <= i[2*W+:W];
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default:
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case (s)
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3: o <= i[3*W+:W];
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4: o <= i[4*W+:W];
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5: o <= i[5*W+:W];
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default:
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case (s)
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6: o <= i[6*W+:W];
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default: o <= i[7*W+:W];
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endcase
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endcase
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endcase
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endcase
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end
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endmodule
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module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[4*W+:W];
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else
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o <= i[5*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[6*W+:W];
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else
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o <= i[7*W+:W];
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endmodule
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module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
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always @*
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if (s[0] == 1'b0)
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if (s[1] == 1'b0)
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if (s[2] == 1'b0)
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o <= i[0*W+:W];
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else
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o <= i[1*W+:W];
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else
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if (s[2] == 1'b0)
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o <= i[2*W+:W];
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else
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o <= i[3*W+:W];
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else
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o <= i[4*W+:W];
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endmodule
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module cliffordwolf_nonexclusive_select (
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input wire x, y, z,
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input wire a, b, c, d,
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output reg o
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);
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always @* begin
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o = a;
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if (x) o = b;
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if (y) o = c;
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if (z) o = d;
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end
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endmodule
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module cliffordwolf_freduce (
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input wire [1:0] s,
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input wire a, b, c, d,
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output reg [3:0] o
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);
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always @* begin
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o = {4{a}};
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if (s == 0) o = {3{b}};
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if (s == 1) o = {2{c}};
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if (s == 2) o = d;
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end
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endmodule
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module case_nonexclusive_select (
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input wire [1:0] x, y,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0: o = b;
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2: o = b;
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1: o = c;
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default: begin
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o = a;
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if (y == 0) o = d;
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if (y == 1) o = e;
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end
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endcase
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end
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endmodule
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module case_nonoverlap (
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input wire [2:0] x,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0, 2: o = b; // Creates $reduce_or
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1: o = c;
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default:
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case (x)
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3: o = d; 4: o = d; // Creates $reduce_or
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5: o = e;
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default: o = 1'b0;
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endcase
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endcase
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end
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endmodule
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module case_overlap (
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input wire [2:0] x,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0, 2: o = b; // Creates $reduce_or
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1: o = c;
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default:
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case (x)
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0: o = 1'b1; // OVERLAP!
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3, 4: o = d; // Creates $reduce_or
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5: o = e;
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default: o = 1'b0;
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endcase
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endcase
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end
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endmodule
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module case_overlap2 (
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input wire [2:0] x,
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input wire a, b, c, d, e,
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output reg o
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);
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always @* begin
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case (x)
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0: o = b; 2: o = b; // Creates $reduce_or
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1: o = c;
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default:
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case (x)
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0: o = d; 2: o = d; // Creates $reduce_or
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3: o = d; 4: o = d; // Creates $reduce_or
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5: o = e;
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default: o = 1'b0;
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endcase
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endcase
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end
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endmodule
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