OpenFPGA

History

AurelienUoU 555570c15e Update Yosys from version 0.7 to version 0.8		2019-05-23 16:03:08 -06:00
..
README	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
example.v	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
example.xdc	Update Yosys from version 0.7 to version 0.8	2019-05-23 16:03:08 -06:00
run.sh	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run_prog.tcl	Update Yosys from version 0.7 to version 0.8	2019-05-23 16:03:08 -06:00
run_vivado.tcl	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00
run_yosys.ys	Add Yosys and update flow_flow Perl Script	2018-11-30 21:14:43 -07:00

README

A simple example design, based on the Digilent BASYS3 board
===========================================================

This example uses Yosys for synthesis and Xilinx Vivado
for place&route and bit-stream creation.

Running Yosys:
  yosys run_yosys.ys

Running Vivado:
  vivado -nolog -nojournal -mode batch -source run_vivado.tcl

Programming board:
  vivado -nolog -nojournal -mode batch -source run_prog.tcl

All of the above:
  bash run.sh