63 lines
1.2 KiB
Verilog
63 lines
1.2 KiB
Verilog
// one of my early test cases was the OpenCores I2C master
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// This is a collection of stripped down code snippets from
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// this core that triggered bugs in early versions of yosys.
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// from i2c_master_bit_ctrl
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module i2c_test01(clk, rst, nReset, al);
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input clk, rst, nReset;
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output reg al;
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reg cmd_stop;
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always @(posedge clk or negedge nReset)
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if (~nReset)
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cmd_stop <= #1 1'b0;
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else if (rst)
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cmd_stop <= #1 1'b0;
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always @(posedge clk or negedge nReset)
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if (~nReset)
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al <= #1 1'b0;
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else if (rst)
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al <= #1 1'b0;
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else
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al <= #1 ~cmd_stop;
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endmodule
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// from i2c_master_bit_ctrl
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module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
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input clk, slave_wait, clk_cnt;
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input cmd;
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output reg cmd_stop;
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reg clk_en;
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output reg [15:0] cnt;
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always @(posedge clk)
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if (~|cnt)
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if (~slave_wait)
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begin
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cnt <= #1 clk_cnt;
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clk_en <= #1 1'b1;
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end
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else
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begin
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cnt <= #1 cnt;
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clk_en <= #1 1'b0;
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end
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else
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begin
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cnt <= #1 cnt - 16'h1;
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clk_en <= #1 1'b0;
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end
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always @(posedge clk)
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if (clk_en)
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cmd_stop <= #1 cmd;
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endmodule
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