tangxifan 539bcba851 [core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types		2023-09-06 17:23:41 -07:00
..
src	[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types	2023-09-06 17:23:41 -07:00
CMakeLists.txt	[lib] create tile config lib and start integration to core	2023-07-14 12:13:31 -07:00