121 lines
3.9 KiB
Bash
121 lines
3.9 KiB
Bash
#! /bin/bash
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# Exit if error occurs
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set -e
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# Make sure a clear start
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default_task='lattice_benchmark'
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pwd_path="$PWD"
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# ========================= Read command argument =========================
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usage() { echo "Usage: $0 [-b <benchmark_name>] [-s] run spice only [-p] run vpr only " 1>&2; exit 1; }
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while getopts ":b:vpr:spice:" o; do
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case "${o}" in
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b)
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bench=${OPTARG};;
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v)
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vpr=1;;
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s)
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spice=1;;
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esac
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done
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# ==========================================================================
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task_name=${bench:-$default_task} # run task defined in argument else run default task
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echo "Running task ${task_name}"
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config_file="$PWD/configs/${task_name}.conf"
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bench_txt="$PWD/benchmarks/List/${task_name}.txt"
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rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv"
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task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}"
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verilog_path="${PWD}/regression_${task_name}"
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config_file_final=$(echo ${config_file/.conf/_final.conf})
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# List of argument passed to FPGA flow
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vpr_config_flags=(
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"-conf ${config_file_final}"
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"-benchmark ${bench_txt}"
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"-rpt ${rpt_file}"
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"-vpr_fpga_verilog_dir ${verilog_path}"
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"-N 10"
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"-K 6"
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"-remove_designs"
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"-ace_d 0.5"
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"-multi_thread 1"
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# "-route_chan_width 10"
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"-vpr_fpga_x2p_rename_illegal_port"
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"-vpr_fpga_verilog"
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"-vpr_fpga_bitstream_generator"
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"-vpr_fpga_verilog_print_autocheck_top_testbench"
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"-vpr_fpga_verilog_include_timing"
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"-vpr_fpga_verilog_include_signal_init"
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"-vpr_fpga_verilog_formal_verification_top_netlist"
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"-fix_route_chan_width"
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# "-vpr_fpga_verilog_include_icarus_simulator"
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"-power"
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"-vpr_fpga_spice spice_taskfile"
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"-vpr_fpga_spice_simulator_path /uusoc/facility/cad_tools/Synopsys/lnis_tools/hspice/P-2019.06/hspice/bin/"
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# "-vpr_fpga_spice_print_top_tb"
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"-vpr_fpga_spice_print_component_tb",
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# "-vpr_fpga_spice_print_grid_tb"
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)
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spice_config_flags=(
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"-conf /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/vpr_fpga_spice_conf/sample.conf"
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"-task /research/ece/lnis/USERS/alacchi/Ganesh/OpenFPGA/fpga_flow/scripts/spice_taskfile_yosys_vpr.txt"
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"-rpt ${rpt_file/.csv/_spice_result.csv}"
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"-multi_thread 10"
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# "-parse_grid_tb"
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"-parse_pb_mux_tb"
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"-parse_cb_mux_tb"
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"-parse_sb_mux_tb"
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"-parse_lut_tb"
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# "-parse_hardlogic_tb"
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)
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#=============== Argument Sanity Check =====================
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#Check if script running in correct (OpenFPGA/fpga_flow) folder
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if [[ $pwd_path != *"OpenFPGA/fpga_flow"* ]]; then
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echo "Error : Execute script from OpenFPGA/fpga_flow project folder"
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exitflag=1
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fi
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#Check if fconfig and benchmark_list file exists
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for filepath in $config_file $bench_txt; do
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if [ ! -f $filepath ]; then
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echo "$filepath File not found!"
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exitflag=1
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fi
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done
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if [ -n "$exitflag" ]; then
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echo "Terminating script . . . . . . "
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exit 1
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fi
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#=======================================================
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#======== Replace variables in config file =============
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#Extract OpenFPGA Project Path and Escape
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OPENFPGAPATHKEYWORD=$(echo "$(echo $pwd_path | sed 's/.OpenFPGA.*$//')/OpenFPGA" | sed 's/\//\\\//g')
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# Create final config file with replaced keywords replaced variables
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sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_file_final
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#==================Clean result, change directory and execute ===============
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cd ${pwd_path}/scripts
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if [[ -n "$vpr" ]]; then
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# Create echo and execute VPR command
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command="perl fpga_flow.pl $(echo ${vpr_config_flags[@]})"
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echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n"
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eval ${command}
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fi
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if [[ -n "$spice" ]]; then
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# Create echo and SPICE Execution
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command="perl run_fpga_spice.pl $(echo ${spice_config_flags[@]})"
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echo -e "\n* * * * * * * * * * * \n"${command} "\n* * * * * * * * * * * \n"
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eval ${command}
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fi
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echo "Netlists successfully generated and simulated"
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exit 0 |