33 lines
1.8 KiB
Plaintext
33 lines
1.8 KiB
Plaintext
# Standard Configuration Example
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[dir_path]
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script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/
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benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example
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# yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys
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yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA/yosys/yosys
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odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe
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cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit
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abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc
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abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc
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mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1
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m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net
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mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2
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vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr
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rpt_dir = /var/tmp/Openfpga/results
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ace_path = OPENFPGAPATHKEYWORD/ace2/ace
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[flow_conf]
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#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr
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flow_type = yosys_vpr
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vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml
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mpack1_abc_stdlib = Not_Required
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m2net_conf = Not_Required
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mpack2_arch = Not_Required
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power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml
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[csv_tags]
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mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf:
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mpack2_tags = BLE Number: | BLE Fill Rate:
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vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles:
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vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff
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