Jingrong Lin 77b188060b Merge branch 'master' into preloading_clean		2024-09-11 11:08:49 +08:00
..
basic_reg_test.sh	Merge branch 'master' into preloading_clean	2024-09-11 11:08:49 +08:00
basic_reg_yosys_only_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_bitstream_reg_test.sh	Update test flow	2024-07-27 23:52:54 -07:00
fpga_sdc_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_spice_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
fpga_verilog_reg_test.sh	[test] add new tests to validate the options for undriven inputs in verilog netlists	2024-08-06 20:58:00 -07:00
iwls_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
micro_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
quicklogic_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00
tcl_reg_test.sh	[script] enable eval mode in tcl reg test	2022-12-02 12:07:27 -08:00
vtr_benchmark_reg_test.sh	[test] now use latest python3 of ubuntu 22.04	2024-05-06 11:44:45 -07:00