628 lines
43 KiB
Verilog
628 lines
43 KiB
Verilog
//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Switch Block [0][0] in FPGA
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// Author: Xifan TANG
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// Organization: EPFL/IC/LSI
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// Date: Thu Nov 15 14:26:04 2018
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Verilog Module of Switch Box[0][0] -----
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module sb_0__0_ (
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//----- BEGIN Global ports -----
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input [0:0] zin,
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input [0:0] clk,
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input [0:0] Reset,
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input [0:0] Set
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//----- END Global ports -----
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,
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//----- Inputs/outputs of top side -----
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output chany_0__1__out_0_,
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input chany_0__1__in_1_,
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output chany_0__1__out_2_,
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input chany_0__1__in_3_,
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output chany_0__1__out_4_,
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input chany_0__1__in_5_,
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output chany_0__1__out_6_,
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input chany_0__1__in_7_,
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output chany_0__1__out_8_,
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input chany_0__1__in_9_,
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output chany_0__1__out_10_,
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input chany_0__1__in_11_,
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output chany_0__1__out_12_,
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input chany_0__1__in_13_,
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output chany_0__1__out_14_,
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input chany_0__1__in_15_,
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output chany_0__1__out_16_,
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input chany_0__1__in_17_,
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output chany_0__1__out_18_,
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input chany_0__1__in_19_,
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output chany_0__1__out_20_,
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input chany_0__1__in_21_,
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output chany_0__1__out_22_,
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input chany_0__1__in_23_,
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output chany_0__1__out_24_,
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input chany_0__1__in_25_,
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output chany_0__1__out_26_,
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input chany_0__1__in_27_,
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output chany_0__1__out_28_,
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input chany_0__1__in_29_,
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input grid_0__1__pin_0__1__1_,
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input grid_0__1__pin_0__1__3_,
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input grid_0__1__pin_0__1__5_,
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input grid_0__1__pin_0__1__7_,
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input grid_0__1__pin_0__1__9_,
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input grid_0__1__pin_0__1__11_,
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input grid_0__1__pin_0__1__13_,
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input grid_0__1__pin_0__1__15_,
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//----- Inputs/outputs of right side -----
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output chanx_1__0__out_0_,
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input chanx_1__0__in_1_,
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output chanx_1__0__out_2_,
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input chanx_1__0__in_3_,
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output chanx_1__0__out_4_,
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input chanx_1__0__in_5_,
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output chanx_1__0__out_6_,
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input chanx_1__0__in_7_,
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output chanx_1__0__out_8_,
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input chanx_1__0__in_9_,
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output chanx_1__0__out_10_,
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input chanx_1__0__in_11_,
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output chanx_1__0__out_12_,
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input chanx_1__0__in_13_,
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output chanx_1__0__out_14_,
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input chanx_1__0__in_15_,
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output chanx_1__0__out_16_,
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input chanx_1__0__in_17_,
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output chanx_1__0__out_18_,
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input chanx_1__0__in_19_,
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output chanx_1__0__out_20_,
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input chanx_1__0__in_21_,
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output chanx_1__0__out_22_,
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input chanx_1__0__in_23_,
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output chanx_1__0__out_24_,
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input chanx_1__0__in_25_,
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output chanx_1__0__out_26_,
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input chanx_1__0__in_27_,
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output chanx_1__0__out_28_,
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input chanx_1__0__in_29_,
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input grid_1__0__pin_0__0__1_,
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input grid_1__0__pin_0__0__3_,
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input grid_1__0__pin_0__0__5_,
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input grid_1__0__pin_0__0__7_,
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input grid_1__0__pin_0__0__9_,
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input grid_1__0__pin_0__0__11_,
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input grid_1__0__pin_0__0__13_,
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input grid_1__0__pin_0__0__15_,
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//----- Inputs/outputs of bottom side -----
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//----- Inputs/outputs of left side -----
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input [0:33] sram_blwl_bl ,
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input [0:33] sram_blwl_wl ,
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input [0:33] sram_blwl_blb );
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//----- top side Multiplexers -----
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wire [0:2] mux_1level_tapbuf_size3_0_inbus;
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assign mux_1level_tapbuf_size3_0_inbus[0] = grid_0__1__pin_0__1__1_;
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assign mux_1level_tapbuf_size3_0_inbus[1] = grid_0__1__pin_0__1__15_;
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assign mux_1level_tapbuf_size3_0_inbus[2] = chanx_1__0__in_3_ ;
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wire [0:2] mux_1level_tapbuf_size3_0_configbus0;
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wire [0:2] mux_1level_tapbuf_size3_0_configbus1;
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wire [0:2] mux_1level_tapbuf_size3_0_sram_blwl_out ;
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wire [0:2] mux_1level_tapbuf_size3_0_sram_blwl_outb ;
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assign mux_1level_tapbuf_size3_0_configbus0[0:2] = sram_blwl_bl[0:2] ;
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assign mux_1level_tapbuf_size3_0_configbus1[0:2] = sram_blwl_wl[0:2] ;
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wire [0:2] mux_1level_tapbuf_size3_0_configbus0_b;
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assign mux_1level_tapbuf_size3_0_configbus0_b[0:2] = sram_blwl_blb[0:2] ;
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mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_0_ (mux_1level_tapbuf_size3_0_inbus, chany_0__1__out_0_ , mux_1level_tapbuf_size3_0_sram_blwl_out[0:2] ,
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mux_1level_tapbuf_size3_0_sram_blwl_outb[0:2] );
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//----- SRAM bits for MUX[0], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----100-----
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sram6T_blwl sram_blwl_0_ (mux_1level_tapbuf_size3_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size3_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[0:0] ,mux_1level_tapbuf_size3_0_configbus0[0:0], mux_1level_tapbuf_size3_0_configbus1[0:0] , mux_1level_tapbuf_size3_0_configbus0_b[0:0] );
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sram6T_blwl sram_blwl_1_ (mux_1level_tapbuf_size3_0_sram_blwl_out[1:1] ,mux_1level_tapbuf_size3_0_sram_blwl_out[1:1] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[1:1] ,mux_1level_tapbuf_size3_0_configbus0[1:1], mux_1level_tapbuf_size3_0_configbus1[1:1] , mux_1level_tapbuf_size3_0_configbus0_b[1:1] );
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sram6T_blwl sram_blwl_2_ (mux_1level_tapbuf_size3_0_sram_blwl_out[2:2] ,mux_1level_tapbuf_size3_0_sram_blwl_out[2:2] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[2:2] ,mux_1level_tapbuf_size3_0_configbus0[2:2], mux_1level_tapbuf_size3_0_configbus1[2:2] , mux_1level_tapbuf_size3_0_configbus0_b[2:2] );
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wire [0:1] mux_1level_tapbuf_size2_1_inbus;
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assign mux_1level_tapbuf_size2_1_inbus[0] = grid_0__1__pin_0__1__1_;
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assign mux_1level_tapbuf_size2_1_inbus[1] = chanx_1__0__in_5_ ;
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wire [3:3] mux_1level_tapbuf_size2_1_configbus0;
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wire [3:3] mux_1level_tapbuf_size2_1_configbus1;
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wire [3:3] mux_1level_tapbuf_size2_1_sram_blwl_out ;
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wire [3:3] mux_1level_tapbuf_size2_1_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_1_configbus0[3:3] = sram_blwl_bl[3:3] ;
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assign mux_1level_tapbuf_size2_1_configbus1[3:3] = sram_blwl_wl[3:3] ;
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wire [3:3] mux_1level_tapbuf_size2_1_configbus0_b;
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assign mux_1level_tapbuf_size2_1_configbus0_b[3:3] = sram_blwl_blb[3:3] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_1_ (mux_1level_tapbuf_size2_1_inbus, chany_0__1__out_2_ , mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] ,
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mux_1level_tapbuf_size2_1_sram_blwl_outb[3:3] );
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//----- SRAM bits for MUX[1], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_3_ (mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_1_sram_blwl_outb[3:3] ,mux_1level_tapbuf_size2_1_configbus0[3:3], mux_1level_tapbuf_size2_1_configbus1[3:3] , mux_1level_tapbuf_size2_1_configbus0_b[3:3] );
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wire [0:1] mux_1level_tapbuf_size2_2_inbus;
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assign mux_1level_tapbuf_size2_2_inbus[0] = grid_0__1__pin_0__1__3_;
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assign mux_1level_tapbuf_size2_2_inbus[1] = chanx_1__0__in_7_ ;
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wire [4:4] mux_1level_tapbuf_size2_2_configbus0;
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wire [4:4] mux_1level_tapbuf_size2_2_configbus1;
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wire [4:4] mux_1level_tapbuf_size2_2_sram_blwl_out ;
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wire [4:4] mux_1level_tapbuf_size2_2_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_2_configbus0[4:4] = sram_blwl_bl[4:4] ;
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assign mux_1level_tapbuf_size2_2_configbus1[4:4] = sram_blwl_wl[4:4] ;
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wire [4:4] mux_1level_tapbuf_size2_2_configbus0_b;
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assign mux_1level_tapbuf_size2_2_configbus0_b[4:4] = sram_blwl_blb[4:4] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_2_ (mux_1level_tapbuf_size2_2_inbus, chany_0__1__out_4_ , mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] ,
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mux_1level_tapbuf_size2_2_sram_blwl_outb[4:4] );
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//----- SRAM bits for MUX[2], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_4_ (mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_2_sram_blwl_outb[4:4] ,mux_1level_tapbuf_size2_2_configbus0[4:4], mux_1level_tapbuf_size2_2_configbus1[4:4] , mux_1level_tapbuf_size2_2_configbus0_b[4:4] );
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wire [0:1] mux_1level_tapbuf_size2_3_inbus;
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assign mux_1level_tapbuf_size2_3_inbus[0] = grid_0__1__pin_0__1__3_;
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assign mux_1level_tapbuf_size2_3_inbus[1] = chanx_1__0__in_9_ ;
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wire [5:5] mux_1level_tapbuf_size2_3_configbus0;
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wire [5:5] mux_1level_tapbuf_size2_3_configbus1;
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wire [5:5] mux_1level_tapbuf_size2_3_sram_blwl_out ;
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wire [5:5] mux_1level_tapbuf_size2_3_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_3_configbus0[5:5] = sram_blwl_bl[5:5] ;
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assign mux_1level_tapbuf_size2_3_configbus1[5:5] = sram_blwl_wl[5:5] ;
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wire [5:5] mux_1level_tapbuf_size2_3_configbus0_b;
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assign mux_1level_tapbuf_size2_3_configbus0_b[5:5] = sram_blwl_blb[5:5] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_3_ (mux_1level_tapbuf_size2_3_inbus, chany_0__1__out_6_ , mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] ,
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mux_1level_tapbuf_size2_3_sram_blwl_outb[5:5] );
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//----- SRAM bits for MUX[3], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_5_ (mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_3_sram_blwl_outb[5:5] ,mux_1level_tapbuf_size2_3_configbus0[5:5], mux_1level_tapbuf_size2_3_configbus1[5:5] , mux_1level_tapbuf_size2_3_configbus0_b[5:5] );
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wire [0:1] mux_1level_tapbuf_size2_4_inbus;
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assign mux_1level_tapbuf_size2_4_inbus[0] = grid_0__1__pin_0__1__5_;
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assign mux_1level_tapbuf_size2_4_inbus[1] = chanx_1__0__in_11_ ;
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wire [6:6] mux_1level_tapbuf_size2_4_configbus0;
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wire [6:6] mux_1level_tapbuf_size2_4_configbus1;
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wire [6:6] mux_1level_tapbuf_size2_4_sram_blwl_out ;
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wire [6:6] mux_1level_tapbuf_size2_4_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_4_configbus0[6:6] = sram_blwl_bl[6:6] ;
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assign mux_1level_tapbuf_size2_4_configbus1[6:6] = sram_blwl_wl[6:6] ;
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wire [6:6] mux_1level_tapbuf_size2_4_configbus0_b;
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assign mux_1level_tapbuf_size2_4_configbus0_b[6:6] = sram_blwl_blb[6:6] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_4_ (mux_1level_tapbuf_size2_4_inbus, chany_0__1__out_8_ , mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] ,
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mux_1level_tapbuf_size2_4_sram_blwl_outb[6:6] );
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//----- SRAM bits for MUX[4], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_6_ (mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_4_sram_blwl_outb[6:6] ,mux_1level_tapbuf_size2_4_configbus0[6:6], mux_1level_tapbuf_size2_4_configbus1[6:6] , mux_1level_tapbuf_size2_4_configbus0_b[6:6] );
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wire [0:1] mux_1level_tapbuf_size2_5_inbus;
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assign mux_1level_tapbuf_size2_5_inbus[0] = grid_0__1__pin_0__1__5_;
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assign mux_1level_tapbuf_size2_5_inbus[1] = chanx_1__0__in_13_ ;
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wire [7:7] mux_1level_tapbuf_size2_5_configbus0;
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wire [7:7] mux_1level_tapbuf_size2_5_configbus1;
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wire [7:7] mux_1level_tapbuf_size2_5_sram_blwl_out ;
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wire [7:7] mux_1level_tapbuf_size2_5_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_5_configbus0[7:7] = sram_blwl_bl[7:7] ;
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assign mux_1level_tapbuf_size2_5_configbus1[7:7] = sram_blwl_wl[7:7] ;
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wire [7:7] mux_1level_tapbuf_size2_5_configbus0_b;
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assign mux_1level_tapbuf_size2_5_configbus0_b[7:7] = sram_blwl_blb[7:7] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_5_ (mux_1level_tapbuf_size2_5_inbus, chany_0__1__out_10_ , mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] ,
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mux_1level_tapbuf_size2_5_sram_blwl_outb[7:7] );
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//----- SRAM bits for MUX[5], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_7_ (mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_5_sram_blwl_outb[7:7] ,mux_1level_tapbuf_size2_5_configbus0[7:7], mux_1level_tapbuf_size2_5_configbus1[7:7] , mux_1level_tapbuf_size2_5_configbus0_b[7:7] );
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wire [0:1] mux_1level_tapbuf_size2_6_inbus;
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assign mux_1level_tapbuf_size2_6_inbus[0] = grid_0__1__pin_0__1__7_;
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assign mux_1level_tapbuf_size2_6_inbus[1] = chanx_1__0__in_15_ ;
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wire [8:8] mux_1level_tapbuf_size2_6_configbus0;
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wire [8:8] mux_1level_tapbuf_size2_6_configbus1;
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wire [8:8] mux_1level_tapbuf_size2_6_sram_blwl_out ;
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wire [8:8] mux_1level_tapbuf_size2_6_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_6_configbus0[8:8] = sram_blwl_bl[8:8] ;
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assign mux_1level_tapbuf_size2_6_configbus1[8:8] = sram_blwl_wl[8:8] ;
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wire [8:8] mux_1level_tapbuf_size2_6_configbus0_b;
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assign mux_1level_tapbuf_size2_6_configbus0_b[8:8] = sram_blwl_blb[8:8] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_6_ (mux_1level_tapbuf_size2_6_inbus, chany_0__1__out_12_ , mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] ,
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mux_1level_tapbuf_size2_6_sram_blwl_outb[8:8] );
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//----- SRAM bits for MUX[6], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_8_ (mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_6_sram_blwl_outb[8:8] ,mux_1level_tapbuf_size2_6_configbus0[8:8], mux_1level_tapbuf_size2_6_configbus1[8:8] , mux_1level_tapbuf_size2_6_configbus0_b[8:8] );
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wire [0:1] mux_1level_tapbuf_size2_7_inbus;
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assign mux_1level_tapbuf_size2_7_inbus[0] = grid_0__1__pin_0__1__7_;
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assign mux_1level_tapbuf_size2_7_inbus[1] = chanx_1__0__in_17_ ;
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wire [9:9] mux_1level_tapbuf_size2_7_configbus0;
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wire [9:9] mux_1level_tapbuf_size2_7_configbus1;
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wire [9:9] mux_1level_tapbuf_size2_7_sram_blwl_out ;
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wire [9:9] mux_1level_tapbuf_size2_7_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_7_configbus0[9:9] = sram_blwl_bl[9:9] ;
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assign mux_1level_tapbuf_size2_7_configbus1[9:9] = sram_blwl_wl[9:9] ;
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wire [9:9] mux_1level_tapbuf_size2_7_configbus0_b;
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assign mux_1level_tapbuf_size2_7_configbus0_b[9:9] = sram_blwl_blb[9:9] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_7_ (mux_1level_tapbuf_size2_7_inbus, chany_0__1__out_14_ , mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] ,
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mux_1level_tapbuf_size2_7_sram_blwl_outb[9:9] );
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//----- SRAM bits for MUX[7], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_9_ (mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_7_sram_blwl_outb[9:9] ,mux_1level_tapbuf_size2_7_configbus0[9:9], mux_1level_tapbuf_size2_7_configbus1[9:9] , mux_1level_tapbuf_size2_7_configbus0_b[9:9] );
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wire [0:1] mux_1level_tapbuf_size2_8_inbus;
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assign mux_1level_tapbuf_size2_8_inbus[0] = grid_0__1__pin_0__1__9_;
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assign mux_1level_tapbuf_size2_8_inbus[1] = chanx_1__0__in_19_ ;
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wire [10:10] mux_1level_tapbuf_size2_8_configbus0;
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wire [10:10] mux_1level_tapbuf_size2_8_configbus1;
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wire [10:10] mux_1level_tapbuf_size2_8_sram_blwl_out ;
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wire [10:10] mux_1level_tapbuf_size2_8_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_8_configbus0[10:10] = sram_blwl_bl[10:10] ;
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assign mux_1level_tapbuf_size2_8_configbus1[10:10] = sram_blwl_wl[10:10] ;
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wire [10:10] mux_1level_tapbuf_size2_8_configbus0_b;
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assign mux_1level_tapbuf_size2_8_configbus0_b[10:10] = sram_blwl_blb[10:10] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_8_ (mux_1level_tapbuf_size2_8_inbus, chany_0__1__out_16_ , mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] ,
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mux_1level_tapbuf_size2_8_sram_blwl_outb[10:10] );
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//----- SRAM bits for MUX[8], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_10_ (mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_8_sram_blwl_outb[10:10] ,mux_1level_tapbuf_size2_8_configbus0[10:10], mux_1level_tapbuf_size2_8_configbus1[10:10] , mux_1level_tapbuf_size2_8_configbus0_b[10:10] );
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wire [0:1] mux_1level_tapbuf_size2_9_inbus;
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assign mux_1level_tapbuf_size2_9_inbus[0] = grid_0__1__pin_0__1__9_;
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assign mux_1level_tapbuf_size2_9_inbus[1] = chanx_1__0__in_21_ ;
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wire [11:11] mux_1level_tapbuf_size2_9_configbus0;
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wire [11:11] mux_1level_tapbuf_size2_9_configbus1;
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wire [11:11] mux_1level_tapbuf_size2_9_sram_blwl_out ;
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wire [11:11] mux_1level_tapbuf_size2_9_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_9_configbus0[11:11] = sram_blwl_bl[11:11] ;
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assign mux_1level_tapbuf_size2_9_configbus1[11:11] = sram_blwl_wl[11:11] ;
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wire [11:11] mux_1level_tapbuf_size2_9_configbus0_b;
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assign mux_1level_tapbuf_size2_9_configbus0_b[11:11] = sram_blwl_blb[11:11] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_9_ (mux_1level_tapbuf_size2_9_inbus, chany_0__1__out_18_ , mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] ,
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mux_1level_tapbuf_size2_9_sram_blwl_outb[11:11] );
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//----- SRAM bits for MUX[9], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_11_ (mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_9_sram_blwl_outb[11:11] ,mux_1level_tapbuf_size2_9_configbus0[11:11], mux_1level_tapbuf_size2_9_configbus1[11:11] , mux_1level_tapbuf_size2_9_configbus0_b[11:11] );
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wire [0:1] mux_1level_tapbuf_size2_10_inbus;
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assign mux_1level_tapbuf_size2_10_inbus[0] = grid_0__1__pin_0__1__11_;
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assign mux_1level_tapbuf_size2_10_inbus[1] = chanx_1__0__in_23_ ;
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wire [12:12] mux_1level_tapbuf_size2_10_configbus0;
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wire [12:12] mux_1level_tapbuf_size2_10_configbus1;
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wire [12:12] mux_1level_tapbuf_size2_10_sram_blwl_out ;
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wire [12:12] mux_1level_tapbuf_size2_10_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_10_configbus0[12:12] = sram_blwl_bl[12:12] ;
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assign mux_1level_tapbuf_size2_10_configbus1[12:12] = sram_blwl_wl[12:12] ;
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wire [12:12] mux_1level_tapbuf_size2_10_configbus0_b;
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assign mux_1level_tapbuf_size2_10_configbus0_b[12:12] = sram_blwl_blb[12:12] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_10_ (mux_1level_tapbuf_size2_10_inbus, chany_0__1__out_20_ , mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] ,
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mux_1level_tapbuf_size2_10_sram_blwl_outb[12:12] );
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//----- SRAM bits for MUX[10], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_12_ (mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_10_sram_blwl_outb[12:12] ,mux_1level_tapbuf_size2_10_configbus0[12:12], mux_1level_tapbuf_size2_10_configbus1[12:12] , mux_1level_tapbuf_size2_10_configbus0_b[12:12] );
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wire [0:1] mux_1level_tapbuf_size2_11_inbus;
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assign mux_1level_tapbuf_size2_11_inbus[0] = grid_0__1__pin_0__1__11_;
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assign mux_1level_tapbuf_size2_11_inbus[1] = chanx_1__0__in_25_ ;
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wire [13:13] mux_1level_tapbuf_size2_11_configbus0;
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wire [13:13] mux_1level_tapbuf_size2_11_configbus1;
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wire [13:13] mux_1level_tapbuf_size2_11_sram_blwl_out ;
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wire [13:13] mux_1level_tapbuf_size2_11_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_11_configbus0[13:13] = sram_blwl_bl[13:13] ;
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assign mux_1level_tapbuf_size2_11_configbus1[13:13] = sram_blwl_wl[13:13] ;
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wire [13:13] mux_1level_tapbuf_size2_11_configbus0_b;
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assign mux_1level_tapbuf_size2_11_configbus0_b[13:13] = sram_blwl_blb[13:13] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_11_ (mux_1level_tapbuf_size2_11_inbus, chany_0__1__out_22_ , mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] ,
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mux_1level_tapbuf_size2_11_sram_blwl_outb[13:13] );
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//----- SRAM bits for MUX[11], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_13_ (mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_11_sram_blwl_outb[13:13] ,mux_1level_tapbuf_size2_11_configbus0[13:13], mux_1level_tapbuf_size2_11_configbus1[13:13] , mux_1level_tapbuf_size2_11_configbus0_b[13:13] );
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wire [0:1] mux_1level_tapbuf_size2_12_inbus;
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assign mux_1level_tapbuf_size2_12_inbus[0] = grid_0__1__pin_0__1__13_;
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assign mux_1level_tapbuf_size2_12_inbus[1] = chanx_1__0__in_27_ ;
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wire [14:14] mux_1level_tapbuf_size2_12_configbus0;
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wire [14:14] mux_1level_tapbuf_size2_12_configbus1;
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wire [14:14] mux_1level_tapbuf_size2_12_sram_blwl_out ;
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wire [14:14] mux_1level_tapbuf_size2_12_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_12_configbus0[14:14] = sram_blwl_bl[14:14] ;
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assign mux_1level_tapbuf_size2_12_configbus1[14:14] = sram_blwl_wl[14:14] ;
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wire [14:14] mux_1level_tapbuf_size2_12_configbus0_b;
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assign mux_1level_tapbuf_size2_12_configbus0_b[14:14] = sram_blwl_blb[14:14] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_12_ (mux_1level_tapbuf_size2_12_inbus, chany_0__1__out_24_ , mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] ,
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mux_1level_tapbuf_size2_12_sram_blwl_outb[14:14] );
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//----- SRAM bits for MUX[12], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_14_ (mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_12_sram_blwl_outb[14:14] ,mux_1level_tapbuf_size2_12_configbus0[14:14], mux_1level_tapbuf_size2_12_configbus1[14:14] , mux_1level_tapbuf_size2_12_configbus0_b[14:14] );
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wire [0:1] mux_1level_tapbuf_size2_13_inbus;
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assign mux_1level_tapbuf_size2_13_inbus[0] = grid_0__1__pin_0__1__13_;
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assign mux_1level_tapbuf_size2_13_inbus[1] = chanx_1__0__in_29_ ;
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wire [15:15] mux_1level_tapbuf_size2_13_configbus0;
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wire [15:15] mux_1level_tapbuf_size2_13_configbus1;
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wire [15:15] mux_1level_tapbuf_size2_13_sram_blwl_out ;
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wire [15:15] mux_1level_tapbuf_size2_13_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_13_configbus0[15:15] = sram_blwl_bl[15:15] ;
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assign mux_1level_tapbuf_size2_13_configbus1[15:15] = sram_blwl_wl[15:15] ;
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wire [15:15] mux_1level_tapbuf_size2_13_configbus0_b;
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assign mux_1level_tapbuf_size2_13_configbus0_b[15:15] = sram_blwl_blb[15:15] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_13_ (mux_1level_tapbuf_size2_13_inbus, chany_0__1__out_26_ , mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] ,
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mux_1level_tapbuf_size2_13_sram_blwl_outb[15:15] );
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//----- SRAM bits for MUX[13], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_15_ (mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_13_sram_blwl_outb[15:15] ,mux_1level_tapbuf_size2_13_configbus0[15:15], mux_1level_tapbuf_size2_13_configbus1[15:15] , mux_1level_tapbuf_size2_13_configbus0_b[15:15] );
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wire [0:1] mux_1level_tapbuf_size2_14_inbus;
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assign mux_1level_tapbuf_size2_14_inbus[0] = grid_0__1__pin_0__1__15_;
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assign mux_1level_tapbuf_size2_14_inbus[1] = chanx_1__0__in_1_ ;
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wire [16:16] mux_1level_tapbuf_size2_14_configbus0;
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wire [16:16] mux_1level_tapbuf_size2_14_configbus1;
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wire [16:16] mux_1level_tapbuf_size2_14_sram_blwl_out ;
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wire [16:16] mux_1level_tapbuf_size2_14_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_14_configbus0[16:16] = sram_blwl_bl[16:16] ;
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assign mux_1level_tapbuf_size2_14_configbus1[16:16] = sram_blwl_wl[16:16] ;
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wire [16:16] mux_1level_tapbuf_size2_14_configbus0_b;
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assign mux_1level_tapbuf_size2_14_configbus0_b[16:16] = sram_blwl_blb[16:16] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_14_ (mux_1level_tapbuf_size2_14_inbus, chany_0__1__out_28_ , mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] ,
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mux_1level_tapbuf_size2_14_sram_blwl_outb[16:16] );
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//----- SRAM bits for MUX[14], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_16_ (mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_14_sram_blwl_outb[16:16] ,mux_1level_tapbuf_size2_14_configbus0[16:16], mux_1level_tapbuf_size2_14_configbus1[16:16] , mux_1level_tapbuf_size2_14_configbus0_b[16:16] );
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//----- right side Multiplexers -----
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wire [0:2] mux_1level_tapbuf_size3_15_inbus;
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assign mux_1level_tapbuf_size3_15_inbus[0] = grid_1__0__pin_0__0__1_;
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assign mux_1level_tapbuf_size3_15_inbus[1] = grid_1__0__pin_0__0__15_;
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assign mux_1level_tapbuf_size3_15_inbus[2] = chany_0__1__in_29_ ;
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wire [17:19] mux_1level_tapbuf_size3_15_configbus0;
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wire [17:19] mux_1level_tapbuf_size3_15_configbus1;
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wire [17:19] mux_1level_tapbuf_size3_15_sram_blwl_out ;
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wire [17:19] mux_1level_tapbuf_size3_15_sram_blwl_outb ;
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assign mux_1level_tapbuf_size3_15_configbus0[17:19] = sram_blwl_bl[17:19] ;
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assign mux_1level_tapbuf_size3_15_configbus1[17:19] = sram_blwl_wl[17:19] ;
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wire [17:19] mux_1level_tapbuf_size3_15_configbus0_b;
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assign mux_1level_tapbuf_size3_15_configbus0_b[17:19] = sram_blwl_blb[17:19] ;
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mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_15_ (mux_1level_tapbuf_size3_15_inbus, chanx_1__0__out_0_ , mux_1level_tapbuf_size3_15_sram_blwl_out[17:19] ,
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mux_1level_tapbuf_size3_15_sram_blwl_outb[17:19] );
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//----- SRAM bits for MUX[15], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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|
//-----100-----
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sram6T_blwl sram_blwl_17_ (mux_1level_tapbuf_size3_15_sram_blwl_out[17:17] ,mux_1level_tapbuf_size3_15_sram_blwl_out[17:17] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[17:17] ,mux_1level_tapbuf_size3_15_configbus0[17:17], mux_1level_tapbuf_size3_15_configbus1[17:17] , mux_1level_tapbuf_size3_15_configbus0_b[17:17] );
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sram6T_blwl sram_blwl_18_ (mux_1level_tapbuf_size3_15_sram_blwl_out[18:18] ,mux_1level_tapbuf_size3_15_sram_blwl_out[18:18] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[18:18] ,mux_1level_tapbuf_size3_15_configbus0[18:18], mux_1level_tapbuf_size3_15_configbus1[18:18] , mux_1level_tapbuf_size3_15_configbus0_b[18:18] );
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sram6T_blwl sram_blwl_19_ (mux_1level_tapbuf_size3_15_sram_blwl_out[19:19] ,mux_1level_tapbuf_size3_15_sram_blwl_out[19:19] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[19:19] ,mux_1level_tapbuf_size3_15_configbus0[19:19], mux_1level_tapbuf_size3_15_configbus1[19:19] , mux_1level_tapbuf_size3_15_configbus0_b[19:19] );
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wire [0:1] mux_1level_tapbuf_size2_16_inbus;
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|
assign mux_1level_tapbuf_size2_16_inbus[0] = grid_1__0__pin_0__0__1_;
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|
assign mux_1level_tapbuf_size2_16_inbus[1] = chany_0__1__in_1_ ;
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wire [20:20] mux_1level_tapbuf_size2_16_configbus0;
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wire [20:20] mux_1level_tapbuf_size2_16_configbus1;
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wire [20:20] mux_1level_tapbuf_size2_16_sram_blwl_out ;
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|
wire [20:20] mux_1level_tapbuf_size2_16_sram_blwl_outb ;
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|
assign mux_1level_tapbuf_size2_16_configbus0[20:20] = sram_blwl_bl[20:20] ;
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|
assign mux_1level_tapbuf_size2_16_configbus1[20:20] = sram_blwl_wl[20:20] ;
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wire [20:20] mux_1level_tapbuf_size2_16_configbus0_b;
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|
assign mux_1level_tapbuf_size2_16_configbus0_b[20:20] = sram_blwl_blb[20:20] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_16_ (mux_1level_tapbuf_size2_16_inbus, chanx_1__0__out_2_ , mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] ,
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mux_1level_tapbuf_size2_16_sram_blwl_outb[20:20] );
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|
//----- SRAM bits for MUX[16], level=1, select_path_id=0. -----
|
|
//----- From LSB(LEFT) TO MSB (RIGHT) -----
|
|
//-----1-----
|
|
sram6T_blwl sram_blwl_20_ (mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_16_sram_blwl_outb[20:20] ,mux_1level_tapbuf_size2_16_configbus0[20:20], mux_1level_tapbuf_size2_16_configbus1[20:20] , mux_1level_tapbuf_size2_16_configbus0_b[20:20] );
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|
wire [0:1] mux_1level_tapbuf_size2_17_inbus;
|
|
assign mux_1level_tapbuf_size2_17_inbus[0] = grid_1__0__pin_0__0__3_;
|
|
assign mux_1level_tapbuf_size2_17_inbus[1] = chany_0__1__in_3_ ;
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wire [21:21] mux_1level_tapbuf_size2_17_configbus0;
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wire [21:21] mux_1level_tapbuf_size2_17_configbus1;
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wire [21:21] mux_1level_tapbuf_size2_17_sram_blwl_out ;
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wire [21:21] mux_1level_tapbuf_size2_17_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_17_configbus0[21:21] = sram_blwl_bl[21:21] ;
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assign mux_1level_tapbuf_size2_17_configbus1[21:21] = sram_blwl_wl[21:21] ;
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wire [21:21] mux_1level_tapbuf_size2_17_configbus0_b;
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assign mux_1level_tapbuf_size2_17_configbus0_b[21:21] = sram_blwl_blb[21:21] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_17_ (mux_1level_tapbuf_size2_17_inbus, chanx_1__0__out_4_ , mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] ,
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mux_1level_tapbuf_size2_17_sram_blwl_outb[21:21] );
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//----- SRAM bits for MUX[17], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_21_ (mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_17_sram_blwl_outb[21:21] ,mux_1level_tapbuf_size2_17_configbus0[21:21], mux_1level_tapbuf_size2_17_configbus1[21:21] , mux_1level_tapbuf_size2_17_configbus0_b[21:21] );
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wire [0:1] mux_1level_tapbuf_size2_18_inbus;
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assign mux_1level_tapbuf_size2_18_inbus[0] = grid_1__0__pin_0__0__3_;
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assign mux_1level_tapbuf_size2_18_inbus[1] = chany_0__1__in_5_ ;
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wire [22:22] mux_1level_tapbuf_size2_18_configbus0;
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wire [22:22] mux_1level_tapbuf_size2_18_configbus1;
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wire [22:22] mux_1level_tapbuf_size2_18_sram_blwl_out ;
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wire [22:22] mux_1level_tapbuf_size2_18_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_18_configbus0[22:22] = sram_blwl_bl[22:22] ;
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assign mux_1level_tapbuf_size2_18_configbus1[22:22] = sram_blwl_wl[22:22] ;
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wire [22:22] mux_1level_tapbuf_size2_18_configbus0_b;
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assign mux_1level_tapbuf_size2_18_configbus0_b[22:22] = sram_blwl_blb[22:22] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_18_ (mux_1level_tapbuf_size2_18_inbus, chanx_1__0__out_6_ , mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] ,
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mux_1level_tapbuf_size2_18_sram_blwl_outb[22:22] );
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//----- SRAM bits for MUX[18], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_22_ (mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_18_sram_blwl_outb[22:22] ,mux_1level_tapbuf_size2_18_configbus0[22:22], mux_1level_tapbuf_size2_18_configbus1[22:22] , mux_1level_tapbuf_size2_18_configbus0_b[22:22] );
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wire [0:1] mux_1level_tapbuf_size2_19_inbus;
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assign mux_1level_tapbuf_size2_19_inbus[0] = grid_1__0__pin_0__0__5_;
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assign mux_1level_tapbuf_size2_19_inbus[1] = chany_0__1__in_7_ ;
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wire [23:23] mux_1level_tapbuf_size2_19_configbus0;
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wire [23:23] mux_1level_tapbuf_size2_19_configbus1;
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wire [23:23] mux_1level_tapbuf_size2_19_sram_blwl_out ;
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wire [23:23] mux_1level_tapbuf_size2_19_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_19_configbus0[23:23] = sram_blwl_bl[23:23] ;
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assign mux_1level_tapbuf_size2_19_configbus1[23:23] = sram_blwl_wl[23:23] ;
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wire [23:23] mux_1level_tapbuf_size2_19_configbus0_b;
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assign mux_1level_tapbuf_size2_19_configbus0_b[23:23] = sram_blwl_blb[23:23] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_19_ (mux_1level_tapbuf_size2_19_inbus, chanx_1__0__out_8_ , mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] ,
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mux_1level_tapbuf_size2_19_sram_blwl_outb[23:23] );
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//----- SRAM bits for MUX[19], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_23_ (mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_19_sram_blwl_outb[23:23] ,mux_1level_tapbuf_size2_19_configbus0[23:23], mux_1level_tapbuf_size2_19_configbus1[23:23] , mux_1level_tapbuf_size2_19_configbus0_b[23:23] );
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wire [0:1] mux_1level_tapbuf_size2_20_inbus;
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assign mux_1level_tapbuf_size2_20_inbus[0] = grid_1__0__pin_0__0__5_;
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assign mux_1level_tapbuf_size2_20_inbus[1] = chany_0__1__in_9_ ;
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wire [24:24] mux_1level_tapbuf_size2_20_configbus0;
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wire [24:24] mux_1level_tapbuf_size2_20_configbus1;
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wire [24:24] mux_1level_tapbuf_size2_20_sram_blwl_out ;
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wire [24:24] mux_1level_tapbuf_size2_20_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_20_configbus0[24:24] = sram_blwl_bl[24:24] ;
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assign mux_1level_tapbuf_size2_20_configbus1[24:24] = sram_blwl_wl[24:24] ;
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wire [24:24] mux_1level_tapbuf_size2_20_configbus0_b;
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assign mux_1level_tapbuf_size2_20_configbus0_b[24:24] = sram_blwl_blb[24:24] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_20_ (mux_1level_tapbuf_size2_20_inbus, chanx_1__0__out_10_ , mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] ,
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mux_1level_tapbuf_size2_20_sram_blwl_outb[24:24] );
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//----- SRAM bits for MUX[20], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_24_ (mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_20_sram_blwl_outb[24:24] ,mux_1level_tapbuf_size2_20_configbus0[24:24], mux_1level_tapbuf_size2_20_configbus1[24:24] , mux_1level_tapbuf_size2_20_configbus0_b[24:24] );
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wire [0:1] mux_1level_tapbuf_size2_21_inbus;
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assign mux_1level_tapbuf_size2_21_inbus[0] = grid_1__0__pin_0__0__7_;
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assign mux_1level_tapbuf_size2_21_inbus[1] = chany_0__1__in_11_ ;
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wire [25:25] mux_1level_tapbuf_size2_21_configbus0;
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wire [25:25] mux_1level_tapbuf_size2_21_configbus1;
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wire [25:25] mux_1level_tapbuf_size2_21_sram_blwl_out ;
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wire [25:25] mux_1level_tapbuf_size2_21_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_21_configbus0[25:25] = sram_blwl_bl[25:25] ;
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assign mux_1level_tapbuf_size2_21_configbus1[25:25] = sram_blwl_wl[25:25] ;
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wire [25:25] mux_1level_tapbuf_size2_21_configbus0_b;
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assign mux_1level_tapbuf_size2_21_configbus0_b[25:25] = sram_blwl_blb[25:25] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_21_ (mux_1level_tapbuf_size2_21_inbus, chanx_1__0__out_12_ , mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] ,
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mux_1level_tapbuf_size2_21_sram_blwl_outb[25:25] );
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//----- SRAM bits for MUX[21], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_25_ (mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_21_sram_blwl_outb[25:25] ,mux_1level_tapbuf_size2_21_configbus0[25:25], mux_1level_tapbuf_size2_21_configbus1[25:25] , mux_1level_tapbuf_size2_21_configbus0_b[25:25] );
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wire [0:1] mux_1level_tapbuf_size2_22_inbus;
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assign mux_1level_tapbuf_size2_22_inbus[0] = grid_1__0__pin_0__0__7_;
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assign mux_1level_tapbuf_size2_22_inbus[1] = chany_0__1__in_13_ ;
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wire [26:26] mux_1level_tapbuf_size2_22_configbus0;
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wire [26:26] mux_1level_tapbuf_size2_22_configbus1;
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wire [26:26] mux_1level_tapbuf_size2_22_sram_blwl_out ;
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wire [26:26] mux_1level_tapbuf_size2_22_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_22_configbus0[26:26] = sram_blwl_bl[26:26] ;
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assign mux_1level_tapbuf_size2_22_configbus1[26:26] = sram_blwl_wl[26:26] ;
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wire [26:26] mux_1level_tapbuf_size2_22_configbus0_b;
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assign mux_1level_tapbuf_size2_22_configbus0_b[26:26] = sram_blwl_blb[26:26] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_22_ (mux_1level_tapbuf_size2_22_inbus, chanx_1__0__out_14_ , mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] ,
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mux_1level_tapbuf_size2_22_sram_blwl_outb[26:26] );
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//----- SRAM bits for MUX[22], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_26_ (mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_22_sram_blwl_outb[26:26] ,mux_1level_tapbuf_size2_22_configbus0[26:26], mux_1level_tapbuf_size2_22_configbus1[26:26] , mux_1level_tapbuf_size2_22_configbus0_b[26:26] );
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wire [0:1] mux_1level_tapbuf_size2_23_inbus;
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assign mux_1level_tapbuf_size2_23_inbus[0] = grid_1__0__pin_0__0__9_;
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assign mux_1level_tapbuf_size2_23_inbus[1] = chany_0__1__in_15_ ;
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wire [27:27] mux_1level_tapbuf_size2_23_configbus0;
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wire [27:27] mux_1level_tapbuf_size2_23_configbus1;
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wire [27:27] mux_1level_tapbuf_size2_23_sram_blwl_out ;
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wire [27:27] mux_1level_tapbuf_size2_23_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_23_configbus0[27:27] = sram_blwl_bl[27:27] ;
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assign mux_1level_tapbuf_size2_23_configbus1[27:27] = sram_blwl_wl[27:27] ;
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wire [27:27] mux_1level_tapbuf_size2_23_configbus0_b;
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assign mux_1level_tapbuf_size2_23_configbus0_b[27:27] = sram_blwl_blb[27:27] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_23_ (mux_1level_tapbuf_size2_23_inbus, chanx_1__0__out_16_ , mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] ,
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mux_1level_tapbuf_size2_23_sram_blwl_outb[27:27] );
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//----- SRAM bits for MUX[23], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_27_ (mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_23_sram_blwl_outb[27:27] ,mux_1level_tapbuf_size2_23_configbus0[27:27], mux_1level_tapbuf_size2_23_configbus1[27:27] , mux_1level_tapbuf_size2_23_configbus0_b[27:27] );
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wire [0:1] mux_1level_tapbuf_size2_24_inbus;
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assign mux_1level_tapbuf_size2_24_inbus[0] = grid_1__0__pin_0__0__9_;
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assign mux_1level_tapbuf_size2_24_inbus[1] = chany_0__1__in_17_ ;
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wire [28:28] mux_1level_tapbuf_size2_24_configbus0;
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wire [28:28] mux_1level_tapbuf_size2_24_configbus1;
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wire [28:28] mux_1level_tapbuf_size2_24_sram_blwl_out ;
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wire [28:28] mux_1level_tapbuf_size2_24_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_24_configbus0[28:28] = sram_blwl_bl[28:28] ;
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assign mux_1level_tapbuf_size2_24_configbus1[28:28] = sram_blwl_wl[28:28] ;
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wire [28:28] mux_1level_tapbuf_size2_24_configbus0_b;
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assign mux_1level_tapbuf_size2_24_configbus0_b[28:28] = sram_blwl_blb[28:28] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_24_ (mux_1level_tapbuf_size2_24_inbus, chanx_1__0__out_18_ , mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] ,
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mux_1level_tapbuf_size2_24_sram_blwl_outb[28:28] );
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//----- SRAM bits for MUX[24], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
|
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//-----1-----
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sram6T_blwl sram_blwl_28_ (mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_24_sram_blwl_outb[28:28] ,mux_1level_tapbuf_size2_24_configbus0[28:28], mux_1level_tapbuf_size2_24_configbus1[28:28] , mux_1level_tapbuf_size2_24_configbus0_b[28:28] );
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wire [0:1] mux_1level_tapbuf_size2_25_inbus;
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assign mux_1level_tapbuf_size2_25_inbus[0] = grid_1__0__pin_0__0__11_;
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assign mux_1level_tapbuf_size2_25_inbus[1] = chany_0__1__in_19_ ;
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wire [29:29] mux_1level_tapbuf_size2_25_configbus0;
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wire [29:29] mux_1level_tapbuf_size2_25_configbus1;
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wire [29:29] mux_1level_tapbuf_size2_25_sram_blwl_out ;
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wire [29:29] mux_1level_tapbuf_size2_25_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_25_configbus0[29:29] = sram_blwl_bl[29:29] ;
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assign mux_1level_tapbuf_size2_25_configbus1[29:29] = sram_blwl_wl[29:29] ;
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wire [29:29] mux_1level_tapbuf_size2_25_configbus0_b;
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assign mux_1level_tapbuf_size2_25_configbus0_b[29:29] = sram_blwl_blb[29:29] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_25_ (mux_1level_tapbuf_size2_25_inbus, chanx_1__0__out_20_ , mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] ,
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mux_1level_tapbuf_size2_25_sram_blwl_outb[29:29] );
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//----- SRAM bits for MUX[25], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
|
|
//-----1-----
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sram6T_blwl sram_blwl_29_ (mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_25_sram_blwl_outb[29:29] ,mux_1level_tapbuf_size2_25_configbus0[29:29], mux_1level_tapbuf_size2_25_configbus1[29:29] , mux_1level_tapbuf_size2_25_configbus0_b[29:29] );
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wire [0:1] mux_1level_tapbuf_size2_26_inbus;
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assign mux_1level_tapbuf_size2_26_inbus[0] = grid_1__0__pin_0__0__11_;
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assign mux_1level_tapbuf_size2_26_inbus[1] = chany_0__1__in_21_ ;
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wire [30:30] mux_1level_tapbuf_size2_26_configbus0;
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wire [30:30] mux_1level_tapbuf_size2_26_configbus1;
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wire [30:30] mux_1level_tapbuf_size2_26_sram_blwl_out ;
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|
wire [30:30] mux_1level_tapbuf_size2_26_sram_blwl_outb ;
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|
assign mux_1level_tapbuf_size2_26_configbus0[30:30] = sram_blwl_bl[30:30] ;
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|
assign mux_1level_tapbuf_size2_26_configbus1[30:30] = sram_blwl_wl[30:30] ;
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|
wire [30:30] mux_1level_tapbuf_size2_26_configbus0_b;
|
|
assign mux_1level_tapbuf_size2_26_configbus0_b[30:30] = sram_blwl_blb[30:30] ;
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|
mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_26_ (mux_1level_tapbuf_size2_26_inbus, chanx_1__0__out_22_ , mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] ,
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mux_1level_tapbuf_size2_26_sram_blwl_outb[30:30] );
|
|
//----- SRAM bits for MUX[26], level=1, select_path_id=0. -----
|
|
//----- From LSB(LEFT) TO MSB (RIGHT) -----
|
|
//-----1-----
|
|
sram6T_blwl sram_blwl_30_ (mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_26_sram_blwl_outb[30:30] ,mux_1level_tapbuf_size2_26_configbus0[30:30], mux_1level_tapbuf_size2_26_configbus1[30:30] , mux_1level_tapbuf_size2_26_configbus0_b[30:30] );
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wire [0:1] mux_1level_tapbuf_size2_27_inbus;
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|
assign mux_1level_tapbuf_size2_27_inbus[0] = grid_1__0__pin_0__0__13_;
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|
assign mux_1level_tapbuf_size2_27_inbus[1] = chany_0__1__in_23_ ;
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|
wire [31:31] mux_1level_tapbuf_size2_27_configbus0;
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|
wire [31:31] mux_1level_tapbuf_size2_27_configbus1;
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|
wire [31:31] mux_1level_tapbuf_size2_27_sram_blwl_out ;
|
|
wire [31:31] mux_1level_tapbuf_size2_27_sram_blwl_outb ;
|
|
assign mux_1level_tapbuf_size2_27_configbus0[31:31] = sram_blwl_bl[31:31] ;
|
|
assign mux_1level_tapbuf_size2_27_configbus1[31:31] = sram_blwl_wl[31:31] ;
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|
wire [31:31] mux_1level_tapbuf_size2_27_configbus0_b;
|
|
assign mux_1level_tapbuf_size2_27_configbus0_b[31:31] = sram_blwl_blb[31:31] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_27_ (mux_1level_tapbuf_size2_27_inbus, chanx_1__0__out_24_ , mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] ,
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mux_1level_tapbuf_size2_27_sram_blwl_outb[31:31] );
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//----- SRAM bits for MUX[27], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_31_ (mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_27_sram_blwl_outb[31:31] ,mux_1level_tapbuf_size2_27_configbus0[31:31], mux_1level_tapbuf_size2_27_configbus1[31:31] , mux_1level_tapbuf_size2_27_configbus0_b[31:31] );
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wire [0:1] mux_1level_tapbuf_size2_28_inbus;
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assign mux_1level_tapbuf_size2_28_inbus[0] = grid_1__0__pin_0__0__13_;
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assign mux_1level_tapbuf_size2_28_inbus[1] = chany_0__1__in_25_ ;
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wire [32:32] mux_1level_tapbuf_size2_28_configbus0;
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wire [32:32] mux_1level_tapbuf_size2_28_configbus1;
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wire [32:32] mux_1level_tapbuf_size2_28_sram_blwl_out ;
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wire [32:32] mux_1level_tapbuf_size2_28_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_28_configbus0[32:32] = sram_blwl_bl[32:32] ;
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assign mux_1level_tapbuf_size2_28_configbus1[32:32] = sram_blwl_wl[32:32] ;
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wire [32:32] mux_1level_tapbuf_size2_28_configbus0_b;
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assign mux_1level_tapbuf_size2_28_configbus0_b[32:32] = sram_blwl_blb[32:32] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_28_ (mux_1level_tapbuf_size2_28_inbus, chanx_1__0__out_26_ , mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] ,
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mux_1level_tapbuf_size2_28_sram_blwl_outb[32:32] );
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//----- SRAM bits for MUX[28], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_32_ (mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_28_sram_blwl_outb[32:32] ,mux_1level_tapbuf_size2_28_configbus0[32:32], mux_1level_tapbuf_size2_28_configbus1[32:32] , mux_1level_tapbuf_size2_28_configbus0_b[32:32] );
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wire [0:1] mux_1level_tapbuf_size2_29_inbus;
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assign mux_1level_tapbuf_size2_29_inbus[0] = grid_1__0__pin_0__0__15_;
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assign mux_1level_tapbuf_size2_29_inbus[1] = chany_0__1__in_27_ ;
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wire [33:33] mux_1level_tapbuf_size2_29_configbus0;
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wire [33:33] mux_1level_tapbuf_size2_29_configbus1;
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wire [33:33] mux_1level_tapbuf_size2_29_sram_blwl_out ;
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wire [33:33] mux_1level_tapbuf_size2_29_sram_blwl_outb ;
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assign mux_1level_tapbuf_size2_29_configbus0[33:33] = sram_blwl_bl[33:33] ;
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assign mux_1level_tapbuf_size2_29_configbus1[33:33] = sram_blwl_wl[33:33] ;
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wire [33:33] mux_1level_tapbuf_size2_29_configbus0_b;
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assign mux_1level_tapbuf_size2_29_configbus0_b[33:33] = sram_blwl_blb[33:33] ;
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mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_29_ (mux_1level_tapbuf_size2_29_inbus, chanx_1__0__out_28_ , mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] ,
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mux_1level_tapbuf_size2_29_sram_blwl_outb[33:33] );
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//----- SRAM bits for MUX[29], level=1, select_path_id=0. -----
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//----- From LSB(LEFT) TO MSB (RIGHT) -----
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//-----1-----
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sram6T_blwl sram_blwl_33_ (mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_29_sram_blwl_outb[33:33] ,mux_1level_tapbuf_size2_29_configbus0[33:33], mux_1level_tapbuf_size2_29_configbus1[33:33] , mux_1level_tapbuf_size2_29_configbus0_b[33:33] );
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//----- bottom side Multiplexers -----
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//----- left side Multiplexers -----
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endmodule
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//----- END Verilog Module of Switch Box[0][0] -----
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