..
README.md
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml
[Arch] Add openfpga architecture which uses 4 global clocks
2021-01-12 18:00:22 -07:00
k4_N4_40nm_GlobalTile8Clk_cc_openfpga.xml
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
k4_N4_40nm_GlobalTileClk_cc_openfpga.xml
[Arch] Remove port size XML syntax
2021-01-09 16:30:46 -07:00
k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
k4_N4_40nm_bank_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_bank_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_bank_use_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_bank_use_resetb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_bank_use_set_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_bank_use_setb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_cfgscff_openfpga.xml
[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
2021-01-04 17:39:13 -07:00
k4_N4_40nm_cc_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_use_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_use_resetb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_use_set_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_cc_use_setb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_fixed_sim_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_ccff_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_const_input_gnd_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_no_const_input_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_scff_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_use_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_use_resetb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_use_set_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_frame_use_setb_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_bank_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_bank_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_cc_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_cc_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_multi_region_frame_use_both_set_reset_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_powergate_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_40nm_standalone_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N4_no_local_routing_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_N5_pattern_local_routing_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_fracNative_N4_40nm_cc_openfpga.xml
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
k4_frac_N4_40nm_cc_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_fracff_40nm_cc_openfpga.xml
[Arch] Patch architecture due to missing mode bit definition
2021-07-02 11:41:29 -06:00
k4_frac_N4_lut_use_and_switch_40nm_cc_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k4_frac_N4_lutram_40nm_cc_openfpga.xml
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
2021-01-29 10:19:05 -07:00
k4_frac_N8_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Use single-output DFF for a standard cell FPGA
2020-11-06 10:26:39 -07:00
k4_frac_N8_register_scan_chain_embedded_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Bug fix for embedded io arch
2020-11-04 20:52:47 -07:00
k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Update arch using global reset tile port
2021-01-09 18:04:55 -07:00
k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
2021-03-10 22:45:19 -07:00
k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
[Arch] Bug fix in single-mode 8-bit DSP architectures
2021-04-24 13:30:03 -06:00
k4_frac_N8_reset_softadder_register_scan_chain_frac_dsp16_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
add example of setting bistream for hard logic block from eblif
2021-12-14 07:05:15 -08:00
k6_N10_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_N10_intermediate_buffer_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N8_40nm_openfpga.xml
Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev
2020-11-25 17:29:53 -07:00
k6_frac_N8_debuf_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N8_local_encoder_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N8_stdcell_mux_40nm_openfpga.xml
[Arch] Remove QN from stdcell arch
2020-11-06 11:20:13 -07:00
k6_frac_N8_tree_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_chain_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_chain_dpram8K_dsp36_40nm_openfpga.xml
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
k6_frac_N10_adder_chain_dpram8K_dsp36_fracff_40nm_openfpga.xml
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
k6_frac_N10_adder_chain_mem1K_40nm_openfpga.xml
[Arch] Patch architecture to be compatible with pin names of DPRAM cell
2021-04-28 11:28:23 -06:00
k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
[Arch] recover the mem16k arch as it is used in other test cases
2021-04-28 15:05:30 -06:00
k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_column_chain_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_register_chain_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_behavioral_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_local_encoder_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_spyio_40nm_openfpga.xml
[Architecture] Reorganize the cell netlists and update architecture files accordingly
2020-09-25 11:55:28 -06:00
k6_frac_N10_stdcell_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00
k6_frac_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
k6_frac_N10_tree_mux_40nm_openfpga.xml
[Arch] Update OpenFPGA arch for new syntax on I/O
2020-11-04 20:24:02 -07:00