326 lines
11 KiB
C++
326 lines
11 KiB
C++
/******************************************************************************
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* Memember functions for data structure VerilogTestbenchOption
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******************************************************************************/
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#include "verilog_testbench_options.h"
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#include "openfpga_naming.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/**************************************************
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* Public Constructors
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*************************************************/
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VerilogTestbenchOption::VerilogTestbenchOption() {
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output_directory_.clear();
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top_module_ = "top_tb";
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dut_module_ = "fpga_top";
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fabric_netlist_file_path_.clear();
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reference_benchmark_file_path_.clear();
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print_preconfig_top_testbench_ = false;
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print_formal_verification_top_netlist_ = false;
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print_top_testbench_ = false;
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simulation_ini_path_.clear();
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explicit_port_mapping_ = false;
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include_signal_init_ = false;
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default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
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embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
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time_unit_ = 1E-3;
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time_stamp_ = true;
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use_relative_path_ = false;
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simulator_type_ = e_simulator_type::IVERILOG;
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dump_waveform_ = false;
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verbose_output_ = false;
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SIMULATOR_TYPE_STRING_ = {{"iverilog", "vcs"}};
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}
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/**************************************************
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* Public Accessors
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*************************************************/
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std::string VerilogTestbenchOption::output_directory() const {
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return output_directory_;
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}
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std::string VerilogTestbenchOption::dut_module() const { return dut_module_; }
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std::string VerilogTestbenchOption::top_module() const { return top_module_; }
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std::string VerilogTestbenchOption::fabric_netlist_file_path() const {
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return fabric_netlist_file_path_;
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}
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std::string VerilogTestbenchOption::reference_benchmark_file_path() const {
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return reference_benchmark_file_path_;
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}
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bool VerilogTestbenchOption::print_formal_verification_top_netlist() const {
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return print_formal_verification_top_netlist_;
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}
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bool VerilogTestbenchOption::print_preconfig_top_testbench() const {
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return print_preconfig_top_testbench_;
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}
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bool VerilogTestbenchOption::print_top_testbench() const {
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return print_top_testbench_;
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}
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bool VerilogTestbenchOption::fast_configuration() const {
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return fast_configuration_;
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}
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bool VerilogTestbenchOption::print_simulation_ini() const {
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return !simulation_ini_path_.empty();
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}
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std::string VerilogTestbenchOption::simulation_ini_path() const {
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return simulation_ini_path_;
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}
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bool VerilogTestbenchOption::explicit_port_mapping() const {
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return explicit_port_mapping_;
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}
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bool VerilogTestbenchOption::include_signal_init() const {
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return include_signal_init_;
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}
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bool VerilogTestbenchOption::dump_waveform() const { return dump_waveform_; }
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bool VerilogTestbenchOption::no_self_checking() const {
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return reference_benchmark_file_path_.empty();
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}
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e_verilog_default_net_type VerilogTestbenchOption::default_net_type() const {
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return default_net_type_;
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}
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float VerilogTestbenchOption::time_unit() const { return time_unit_; }
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e_embedded_bitstream_hdl_type
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VerilogTestbenchOption::embedded_bitstream_hdl_type() const {
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return embedded_bitstream_hdl_type_;
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}
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bool VerilogTestbenchOption::time_stamp() const { return time_stamp_; }
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bool VerilogTestbenchOption::use_relative_path() const {
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return use_relative_path_;
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}
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bool VerilogTestbenchOption::verbose_output() const { return verbose_output_; }
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VerilogTestbenchOption::e_simulator_type
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VerilogTestbenchOption::simulator_type() const {
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return simulator_type_;
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}
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/******************************************************************************
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* Private Mutators
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******************************************************************************/
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void VerilogTestbenchOption::set_output_directory(
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const std::string& output_dir) {
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output_directory_ = output_dir;
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}
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void VerilogTestbenchOption::set_top_module(const std::string& top_module) {
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/* Precheck: avoid naming conflicts */
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if (top_module == generate_fpga_top_module_name() ||
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top_module == generate_fpga_core_module_name()) {
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VTR_LOG_ERROR(
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"Conflicted module name '%s' as top-levle module! Please avoid [%s|%s]\n",
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top_module.c_str(), generate_fpga_top_module_name().c_str(),
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generate_fpga_core_module_name().c_str());
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exit(1);
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}
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top_module_ = top_module;
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}
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void VerilogTestbenchOption::set_dut_module(const std::string& dut_module) {
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/* Precheck: only accept two legal names */
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if (dut_module != generate_fpga_top_module_name() &&
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dut_module != generate_fpga_core_module_name()) {
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VTR_LOG_ERROR(
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"Invalid module name '%s' for Design Under Test (DUT)! Expect [%s|%s]\n",
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dut_module.c_str(), generate_fpga_top_module_name().c_str(),
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generate_fpga_core_module_name().c_str());
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exit(1);
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}
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dut_module_ = dut_module;
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}
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void VerilogTestbenchOption::set_fabric_netlist_file_path(
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const std::string& fabric_netlist_file_path) {
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fabric_netlist_file_path_ = fabric_netlist_file_path;
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}
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void VerilogTestbenchOption::set_reference_benchmark_file_path(
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const std::string& reference_benchmark_file_path) {
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reference_benchmark_file_path_ = reference_benchmark_file_path;
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/* Chain effect on other options:
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* Enable/disable the print_preconfig_top_testbench and print_top_testbench
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*/
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set_print_preconfig_top_testbench(print_preconfig_top_testbench_);
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set_print_top_testbench(print_top_testbench_);
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}
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void VerilogTestbenchOption::set_print_formal_verification_top_netlist(
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const bool& enabled) {
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print_formal_verification_top_netlist_ = enabled;
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}
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void VerilogTestbenchOption::set_fast_configuration(const bool& enabled) {
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fast_configuration_ = enabled;
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}
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void VerilogTestbenchOption::set_print_preconfig_top_testbench(
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const bool& enabled) {
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print_preconfig_top_testbench_ =
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enabled && (!reference_benchmark_file_path_.empty());
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/* Enable print formal verification top_netlist if this is enabled */
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if (true == print_preconfig_top_testbench_) {
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if (false == print_formal_verification_top_netlist_) {
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VTR_LOG_WARN(
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"Forcely enable to print top-level Verilog netlist in formal "
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"verification purpose as print pre-configured top-level Verilog "
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"testbench is enabled\n");
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print_formal_verification_top_netlist_ = true;
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}
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}
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}
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void VerilogTestbenchOption::set_print_top_testbench(const bool& enabled) {
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print_top_testbench_ = enabled && (!reference_benchmark_file_path_.empty());
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}
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void VerilogTestbenchOption::set_print_simulation_ini(
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const std::string& simulation_ini_path) {
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simulation_ini_path_ = simulation_ini_path;
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}
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void VerilogTestbenchOption::set_explicit_port_mapping(const bool& enabled) {
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explicit_port_mapping_ = enabled;
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}
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void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
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include_signal_init_ = enabled;
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}
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void VerilogTestbenchOption::set_dump_waveform(const bool& enabled) {
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dump_waveform_ = enabled;
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}
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void VerilogTestbenchOption::set_default_net_type(
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const std::string& default_net_type) {
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/* Decode from net type string */;
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if (default_net_type ==
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std::string(
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VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE])) {
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default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
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} else if (default_net_type ==
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std::string(VERILOG_DEFAULT_NET_TYPE_STRING
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[VERILOG_DEFAULT_NET_TYPE_WIRE])) {
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default_net_type_ = VERILOG_DEFAULT_NET_TYPE_WIRE;
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} else {
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VTR_LOG_WARN(
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"Invalid default net type: '%s'! Expect ['%s'|'%s']\n",
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default_net_type.c_str(),
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VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_NONE],
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VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE]);
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}
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}
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void VerilogTestbenchOption::set_embedded_bitstream_hdl_type(
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const std::string& embedded_bitstream_hdl_type) {
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/* Decode from HDL type string */;
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if (embedded_bitstream_hdl_type ==
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std::string(
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EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES])) {
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embedded_bitstream_hdl_type_ = NUM_EMBEDDED_BITSTREAM_HDL_TYPES;
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} else if (embedded_bitstream_hdl_type ==
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std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING
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[EMBEDDED_BITSTREAM_HDL_IVERILOG])) {
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embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_IVERILOG;
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} else if (embedded_bitstream_hdl_type ==
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std::string(EMBEDDED_BITSTREAM_HDL_TYPE_STRING
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[EMBEDDED_BITSTREAM_HDL_MODELSIM])) {
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embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
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} else {
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VTR_LOG_WARN(
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"Invalid embedded bitstream type: '%s'! Expect ['%s'|'%s'|'%s']\n",
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embedded_bitstream_hdl_type.c_str(),
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EMBEDDED_BITSTREAM_HDL_TYPE_STRING[NUM_EMBEDDED_BITSTREAM_HDL_TYPES],
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EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_IVERILOG],
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EMBEDDED_BITSTREAM_HDL_TYPE_STRING[EMBEDDED_BITSTREAM_HDL_MODELSIM]);
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}
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}
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void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
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time_unit_ = time_unit;
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}
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void VerilogTestbenchOption::set_time_stamp(const bool& enabled) {
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time_stamp_ = enabled;
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}
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void VerilogTestbenchOption::set_use_relative_path(const bool& enabled) {
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use_relative_path_ = enabled;
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}
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void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
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verbose_output_ = enabled;
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}
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int VerilogTestbenchOption::set_simulator_type(const std::string& value) {
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simulator_type_ = str2simulator_type(value);
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return valid_simulator_type(simulator_type_);
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}
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std::string VerilogTestbenchOption::simulator_type_all2str() const {
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std::string full_types = "[";
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for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
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itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
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++itype) {
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full_types += std::string(SIMULATOR_TYPE_STRING_[itype]) + std::string("|");
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}
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full_types.pop_back();
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full_types += "]";
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return full_types;
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}
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VerilogTestbenchOption::e_simulator_type
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VerilogTestbenchOption::str2simulator_type(const std::string& type_str,
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const bool& verbose) const {
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for (int itype = size_t(VerilogTestbenchOption::e_simulator_type::IVERILOG);
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itype != size_t(VerilogTestbenchOption::e_simulator_type::NUM_TYPES);
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++itype) {
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if (type_str == std::string(SIMULATOR_TYPE_STRING_[itype])) {
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return static_cast<VerilogTestbenchOption::e_simulator_type>(itype);
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}
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}
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VTR_LOGV_ERROR(verbose, "Invalid simulator type! Expect %s\n",
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simulator_type_all2str().c_str());
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return VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
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}
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std::string VerilogTestbenchOption::simulator_type2str(
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const VerilogTestbenchOption::e_simulator_type& sim_type,
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const bool& verbose) const {
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if (!valid_simulator_type(sim_type)) {
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VTR_LOGV_ERROR(verbose, "Invalid type for simulator! Expect %s\n",
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simulator_type_all2str().c_str());
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return std::string();
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}
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return std::string(SIMULATOR_TYPE_STRING_[size_t(sim_type)]);
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}
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bool VerilogTestbenchOption::valid_simulator_type(
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const VerilogTestbenchOption::e_simulator_type& sim_type) const {
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return sim_type != VerilogTestbenchOption::e_simulator_type::NUM_TYPES;
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}
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} /* end namespace openfpga */
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