86 lines
3.1 KiB
C++
86 lines
3.1 KiB
C++
/********************************************************************
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* This file includes functions to generate Verilog submodules for LUTs
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********************************************************************/
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#include <algorithm>
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#include <string>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "module_manager.h"
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#include "mux_graph.h"
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#include "mux_utils.h"
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#include "openfpga_digest.h"
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#include "openfpga_naming.h"
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#include "verilog_constants.h"
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#include "verilog_lut.h"
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#include "verilog_module_writer.h"
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#include "verilog_writer_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Print Verilog modules for the Look-Up Tables (LUTs)
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* in the circuit library
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********************************************************************/
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void print_verilog_submodule_luts(const ModuleManager& module_manager,
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NetlistManager& netlist_manager,
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const CircuitLibrary& circuit_lib,
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const ModuleNameMap& module_name_map,
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const std::string& submodule_dir,
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const std::string& submodule_dir_name,
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const FabricVerilogOption& options) {
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std::string verilog_fname(LUTS_VERILOG_FILE_NAME);
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std::string verilog_fpath(submodule_dir + verilog_fname);
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std::fstream fp;
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/* Create the file stream */
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fp.open(verilog_fpath, std::fstream::out | std::fstream::trunc);
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/* Check if the file stream if valid or not */
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check_file_stream(verilog_fpath.c_str(), fp);
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/* Create file */
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VTR_LOG("Writing Verilog netlist for LUTs '%s'...", verilog_fpath.c_str());
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print_verilog_file_header(fp, "Look-Up Tables", options.time_stamp());
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/* Search for each LUT circuit model */
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for (const auto& lut_model : circuit_lib.models()) {
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/* Bypass user-defined and non-LUT modules */
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if ((!circuit_lib.model_verilog_netlist(lut_model).empty()) ||
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(CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model))) {
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continue;
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}
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/* Find the module id */
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ModuleId lut_module = module_manager.find_module(
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module_name_map.name(circuit_lib.model_name(lut_model)));
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VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
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FabricVerilogOption curr_options = options;
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curr_options.set_explicit_port_mapping(
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options.explicit_port_mapping() ||
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circuit_lib.dump_explicit_port_map(lut_model));
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write_verilog_module_to_file(fp, module_manager, lut_module, curr_options);
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}
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/* Close the file handler */
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fp.close();
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/* Add fname to the netlist name list */
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NetlistId nlist_id = NetlistId::INVALID();
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if (options.use_relative_path()) {
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nlist_id = netlist_manager.add_netlist(submodule_dir_name + verilog_fname);
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} else {
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nlist_id = netlist_manager.add_netlist(verilog_fpath);
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}
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VTR_ASSERT(nlist_id);
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netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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