AurelienUoU 8366f9e7b7 Update tutorial		2019-07-08 16:18:08 -06:00
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fpga_spice_bench.txt	Add MCNC Benchmarks netlists generation to travis regression test	2019-05-17 15:22:04 -06:00
mcnc_benchmark.txt	Change benchmarks clock name to avoid yosys blif generation issue (adding a clock) + execute pro_blif.pl to correct ace's blif output issue on latches	2019-05-21 17:24:06 -06:00
mcnc_big20.txt	fixed broken fpga flow	2019-06-28 13:07:04 -06:00
tuto_benchmark.txt	Update tutorial	2019-07-08 16:18:08 -06:00