OpenFPGA/openfpga_flow/tasks/fpga_verilog/lut_design
tangxifan 0b473e3454 [test] fixed the bug in single-mode lut testcase 2023-11-14 09:35:26 -08:00
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frac_lut4/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_lut4_and_switch/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_lut4_arith/config [script] now suggest to skip pb_pin_fixup step in example scripts for most test cases 2022-09-29 10:45:27 -07:00
frac_lut6/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
frac_native_lut4/config [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
intermediate_buffer/config [Flow] Rename OpenFPGA shell script folder name to consistent with naming convention 2020-11-22 16:37:19 -07:00
single_mode/config [test] fixed the bug in single-mode lut testcase 2023-11-14 09:35:26 -08:00