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bottom_right_custom_pins/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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fabric_tile_global_tile_clock_io_subtile/config
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[test] add a new test to validate combo: group tile, tile annotation and subtile
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2023-08-18 21:48:40 -07:00 |
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hetero_fabric_tile/config
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[test] now heterogeneous testcases for tile modules pass
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2023-07-27 20:30:32 -07:00 |
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homo_fabric_tile/config
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[test] fixed a bug on the testcase
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2023-07-27 22:02:28 -07:00 |
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homo_fabric_tile_2x2_preconfig/config
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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homo_fabric_tile_4x4_preconfig/config
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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homo_fabric_tile_adder_chain/config
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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homo_fabric_tile_clkntwk/config
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[test] added a new test case to validate clock network when using the tile modules
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2023-07-27 16:39:48 -07:00 |
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homo_fabric_tile_global_tile_clock/config
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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homo_fabric_tile_preconfig/config
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[test] add a new testcase to validate the heterogeneous fpga fabric when using tile modules
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2023-07-27 17:03:02 -07:00 |
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io_subtile/config
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[test] now testcases are using proper arch
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2023-05-03 21:47:21 +08:00 |
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io_subtile_strong/config
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[test] add a new test to validate io subtile support
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2023-08-18 11:13:34 -07:00 |
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tileable_io/config
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[test] now testcases are using proper arch
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2023-05-03 21:47:21 +08:00 |
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top_left_custom_pins/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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top_right_custom_pins/config
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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