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OpenFPGA/openfpga_flow/openfpga_cell_library
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tangxifan f9dc7c1b54 [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells 2021-03-17 15:15:22 -06:00
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spice [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
spice_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
verilog [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells 2021-03-17 15:15:22 -06:00
verilog_testbench [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00