147 lines
5.2 KiB
C
147 lines
5.2 KiB
C
/*
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Global variables
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Key global variables that are used everywhere in VPR:
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clb_net, vpack_net, block, and logical_block
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These variables represent the user netlist in various stages of the CAD flow:
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vpack_net and logical_block for the unclustered netlist pre packing
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clb_net and block for the clustered netlist post packing
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*/
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#ifndef GLOBALS_H
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#define GLOBALS_H
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/********************************************************************
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Checking OS System
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********************************************************************/
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/*#if defined(__WIN32__) || defined(__WIN32) || defined(_WIN32) || defined(WIN32) || defined(__TOS_WIN__) || defined(__WINDOWS__)
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#ifndef __WIN32__
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#define __WIN32__
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#endif
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#else
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#ifndef __UNIX__
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#define __UNIX__
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#endif
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#include <sys/time.h>
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#endif*/
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/********************************************************************
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User Netlist Globals
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********************************************************************/
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/* external-to-complex block nets in the user netlist */
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extern int num_nets;
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extern struct s_net *clb_net;
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/* blocks in the user netlist */
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extern int num_blocks;
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extern struct s_block *block;
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extern int copy_nb_clusters;
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/********************************************************************
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Physical FPGA architecture globals
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*********************************************************************/
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/* x and y dimensions of the FPGA itself, the core of the FPGA is from [1..nx][1..ny], the I/Os form a perimeter surrounding the core */
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extern int nx, ny;
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extern struct s_grid_tile **grid; /* FPGA complex blocks grid [0..nx+1][0..ny+1] */
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/* Special pointers to identify special blocks on an FPGA: I/Os, unused, and default */
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extern t_type_ptr IO_TYPE;
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extern t_type_ptr EMPTY_TYPE;
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extern t_type_ptr FILL_TYPE;
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/* type_descriptors are blocks that can be moved by the placer
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such as: I/Os, CLBs, memories, multipliers, etc
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Different types of physical block are contained in type descriptors
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*/
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extern int num_types;
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extern struct s_type_descriptor *type_descriptors;
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/* name of the blif circuit */
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extern char *blif_circuit_name;
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/* default output name */
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extern char *default_output_name;
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/* Default area of a 1x1 logic tile (excludes routing) on the FPGA */
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extern float grid_logic_tile_area;
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/* Area of a mux transistor for the input connection block */
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extern float ipin_mux_trans_size;
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/*******************************************************************
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Packing related globals
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********************************************************************/
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/* Netlist description data structures. */
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/* User netlist information */
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extern int num_logical_nets, num_logical_blocks;
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extern int num_p_inputs, num_p_outputs;
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extern struct s_net *vpack_net;
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extern struct s_logical_block *logical_block;
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extern struct s_subckt *subckt;
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/* primiary inputs removed from circuit */
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extern struct s_linked_vptr *circuit_p_io_removed;
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/* Relationship between external-to-complex block nets and internal-to-complex block nets */
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extern int *clb_to_vpack_net_mapping; /* [0..num_clb_nets - 1] */
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extern int *vpack_to_clb_net_mapping; /* [0..num_vpack_nets - 1] */
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/*******************************************************************
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Routing related globals
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********************************************************************/
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/* chan_width_x is the x-directed channel; i.e. between rows */
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extern int *chan_width_x, *chan_width_y; /* numerical form */
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/* [0..num_nets-1] of linked list start pointers. Defines the routing. */
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extern struct s_trace **trace_head, **trace_tail;
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/* Structures to define the routing architecture of the FPGA. */
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extern int num_rr_nodes;
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extern t_rr_node *rr_node; /* [0..num_rr_nodes-1] */
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extern int num_rr_indexed_data;
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extern t_rr_indexed_data *rr_indexed_data; /* [0 .. num_rr_indexed_data-1] */
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extern t_ivec ***rr_node_indices;
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extern int **net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */
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extern struct s_switch_inf *switch_inf; /* [0..det_routing_arch.num_switch-1] */
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extern int **rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
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/* the head pointers of structures that are "freed" and used constantly */
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/*struct s_heap *g_heap_free_head;
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struct s_trace *g_trace_free_head;
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struct s_linked_f_pointer *g_linked_f_pointer_free_head;*/
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/*******************************************************************
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Timing related globals
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********************************************************************/
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extern float pb_max_internal_delay; /* biggest internal delay of block */
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extern const t_pb_type *pbtype_max_internal_delay; /* block type with highest internal delay */
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/*******************************************************************
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Clock Network
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********************************************************************/
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extern t_clock_arch * g_clock_arch;
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/* Xifan TANG: FPGA-SPICE and Verilog Generator */
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/* Detailed routing information for each SB and CB */
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extern t_sb** sb_info;
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extern t_cb** cbx_info;
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extern t_cb** cby_info;
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/* Xifan TANG: detailed runtime statistics */
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extern float pack_route_time;
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/* Xifan TANG: clb_to_clb_directs*/
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extern int num_clb2clb_directs;
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extern t_clb_to_clb_directs* clb2clb_direct;
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#endif
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