tangxifan 4b3142c4ee [Architecture File] Patch openfpga architecture with default circuit model definition		2020-08-23 15:13:28 -06:00
..
OpenFPGAShellScripts	disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks	2020-08-19 15:34:59 -06:00
SpiceNetlists	Moved spice and verilog netlist folder location	2019-08-17 01:49:49 -06:00
VerilogNetlists	add Verilog design for fracturable 32k memory	2020-08-18 21:13:46 -06:00
arch_bitstreams	add load architecture bitstream test case and reorganize regression tests in category of openfpga tools	2020-07-27 15:54:46 -06:00
benchmarks	add regression test to track runtime on big fpga devices using practical benchmarks	2020-07-28 12:38:42 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	update fabric key to synchronize with new module/instance naming	2020-07-24 12:55:40 -06:00
misc	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
openfpga_arch	[Architecture File] Patch openfpga architecture with default circuit model definition	2020-08-23 15:13:28 -06:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	now pro_blif.pl can accept customized clock name	2020-08-19 09:43:44 -06:00
tasks	[regression test] Add more tests for thru channels and deploy to CI	2020-08-19 20:11:37 -06:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[regression test] Add more tests for thru channels and deploy to CI	2020-08-19 20:11:37 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00