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module test(a, b, y);
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input [15:0] a, b;
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output [15:0] y;
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wire [7:0] ah = a[15:8], al = a[7:0];
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wire [7:0] bh = b[15:8], bl = b[7:0];
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wire [7:0] th = ah + bh, tl = al + bl;
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wire [15:0] t = {th, tl}, k = t ^ 16'hcd;
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assign y = { k[7:0], k[15:8] };
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endmodule
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