422 lines
14 KiB
C++
422 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_ignore_gold_x = false;
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bool flag_make_outputs = false;
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bool flag_make_outcmp = false;
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bool flag_make_assert = false;
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bool flag_flatten = false;
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log_header(design, "Executing MITER pass (creating miter circuit).\n");
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-ignore_gold_x") {
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flag_ignore_gold_x = true;
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continue;
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}
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if (args[argidx] == "-make_outputs") {
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flag_make_outputs = true;
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continue;
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}
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if (args[argidx] == "-make_outcmp") {
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flag_make_outcmp = true;
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continue;
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}
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if (args[argidx] == "-make_assert") {
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flag_make_assert = true;
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continue;
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}
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if (args[argidx] == "-flatten") {
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flag_flatten = true;
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continue;
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}
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break;
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}
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if (argidx+3 != args.size() || args[argidx].substr(0, 1) == "-")
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that->cmd_error(args, argidx, "command argument error");
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RTLIL::IdString gold_name = RTLIL::escape_id(args[argidx++]);
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RTLIL::IdString gate_name = RTLIL::escape_id(args[argidx++]);
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RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]);
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if (design->modules_.count(gold_name) == 0)
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log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
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if (design->modules_.count(gate_name) == 0)
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log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
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if (design->modules_.count(miter_name) != 0)
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log_cmd_error("There is already a module %s!\n", miter_name.c_str());
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RTLIL::Module *gold_module = design->modules_.at(gold_name);
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RTLIL::Module *gate_module = design->modules_.at(gate_name);
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for (auto &it : gold_module->wires_) {
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RTLIL::Wire *w1 = it.second, *w2;
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if (w1->port_id == 0)
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continue;
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if (gate_module->wires_.count(it.second->name) == 0)
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goto match_gold_port_error;
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w2 = gate_module->wires_.at(it.second->name);
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if (w1->port_input != w2->port_input)
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goto match_gold_port_error;
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if (w1->port_output != w2->port_output)
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goto match_gold_port_error;
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if (w1->width != w2->width)
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goto match_gold_port_error;
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continue;
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match_gold_port_error:
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log_cmd_error("No matching port in gate module was found for %s!\n", it.second->name.c_str());
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}
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for (auto &it : gate_module->wires_) {
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RTLIL::Wire *w1 = it.second, *w2;
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if (w1->port_id == 0)
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continue;
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if (gold_module->wires_.count(it.second->name) == 0)
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goto match_gate_port_error;
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w2 = gold_module->wires_.at(it.second->name);
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if (w1->port_input != w2->port_input)
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goto match_gate_port_error;
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if (w1->port_output != w2->port_output)
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goto match_gate_port_error;
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if (w1->width != w2->width)
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goto match_gate_port_error;
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continue;
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match_gate_port_error:
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log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
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}
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log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
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RTLIL::Module *miter_module = new RTLIL::Module;
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miter_module->name = miter_name;
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design->add(miter_module);
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RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
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RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
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RTLIL::SigSpec all_conditions;
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for (auto &it : gold_module->wires_)
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{
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RTLIL::Wire *w1 = it.second;
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if (w1->port_input)
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{
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RTLIL::Wire *w2 = miter_module->addWire("\\in_" + RTLIL::unescape_id(w1->name), w1->width);
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w2->port_input = true;
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gold_cell->setPort(w1->name, w2);
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gate_cell->setPort(w1->name, w2);
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}
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if (w1->port_output)
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{
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RTLIL::Wire *w2_gold = miter_module->addWire("\\gold_" + RTLIL::unescape_id(w1->name), w1->width);
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w2_gold->port_output = flag_make_outputs;
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RTLIL::Wire *w2_gate = miter_module->addWire("\\gate_" + RTLIL::unescape_id(w1->name), w1->width);
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w2_gate->port_output = flag_make_outputs;
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gold_cell->setPort(w1->name, w2_gold);
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gate_cell->setPort(w1->name, w2_gate);
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RTLIL::SigSpec this_condition;
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if (flag_ignore_gold_x)
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{
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RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w2_gold->width);
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for (int i = 0; i < w2_gold->width; i++) {
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RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, "$eqx");
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eqx_cell->parameters["\\A_WIDTH"] = 1;
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eqx_cell->parameters["\\B_WIDTH"] = 1;
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eqx_cell->parameters["\\Y_WIDTH"] = 1;
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eqx_cell->parameters["\\A_SIGNED"] = 0;
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eqx_cell->parameters["\\B_SIGNED"] = 0;
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eqx_cell->setPort("\\A", RTLIL::SigSpec(w2_gold, i));
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eqx_cell->setPort("\\B", RTLIL::State::Sx);
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eqx_cell->setPort("\\Y", gold_x.extract(i, 1));
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}
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RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w2_gold->width);
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RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w2_gate->width);
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RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, "$or");
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or_gold_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\B_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\Y_WIDTH"] = w2_gold->width;
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or_gold_cell->parameters["\\A_SIGNED"] = 0;
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or_gold_cell->parameters["\\B_SIGNED"] = 0;
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or_gold_cell->setPort("\\A", w2_gold);
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or_gold_cell->setPort("\\B", gold_x);
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or_gold_cell->setPort("\\Y", gold_masked);
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RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, "$or");
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or_gate_cell->parameters["\\A_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\Y_WIDTH"] = w2_gate->width;
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or_gate_cell->parameters["\\A_SIGNED"] = 0;
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or_gate_cell->parameters["\\B_SIGNED"] = 0;
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or_gate_cell->setPort("\\A", w2_gate);
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or_gate_cell->setPort("\\B", gold_x);
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or_gate_cell->setPort("\\Y", gate_masked);
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RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
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eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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eq_cell->parameters["\\Y_WIDTH"] = 1;
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eq_cell->parameters["\\A_SIGNED"] = 0;
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eq_cell->parameters["\\B_SIGNED"] = 0;
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eq_cell->setPort("\\A", gold_masked);
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eq_cell->setPort("\\B", gate_masked);
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eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
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this_condition = eq_cell->getPort("\\Y");
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}
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else
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{
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RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, "$eqx");
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eq_cell->parameters["\\A_WIDTH"] = w2_gold->width;
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eq_cell->parameters["\\B_WIDTH"] = w2_gate->width;
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eq_cell->parameters["\\Y_WIDTH"] = 1;
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eq_cell->parameters["\\A_SIGNED"] = 0;
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eq_cell->parameters["\\B_SIGNED"] = 0;
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eq_cell->setPort("\\A", w2_gold);
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eq_cell->setPort("\\B", w2_gate);
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eq_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
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this_condition = eq_cell->getPort("\\Y");
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}
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if (flag_make_outcmp)
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{
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RTLIL::Wire *w_cmp = miter_module->addWire("\\cmp_" + RTLIL::unescape_id(w1->name));
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w_cmp->port_output = true;
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miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
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}
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all_conditions.append(this_condition);
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}
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}
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if (all_conditions.size() != 1) {
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RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, "$reduce_and");
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reduce_cell->parameters["\\A_WIDTH"] = all_conditions.size();
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reduce_cell->parameters["\\Y_WIDTH"] = 1;
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reduce_cell->parameters["\\A_SIGNED"] = 0;
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reduce_cell->setPort("\\A", all_conditions);
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reduce_cell->setPort("\\Y", miter_module->addWire(NEW_ID));
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all_conditions = reduce_cell->getPort("\\Y");
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}
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if (flag_make_assert) {
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RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, "$assert");
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assert_cell->setPort("\\A", all_conditions);
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assert_cell->setPort("\\EN", RTLIL::SigSpec(1, 1));
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}
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RTLIL::Wire *w_trigger = miter_module->addWire("\\trigger");
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w_trigger->port_output = true;
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RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, "$not");
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not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
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not_cell->parameters["\\A_WIDTH"] = all_conditions.size();
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not_cell->parameters["\\Y_WIDTH"] = w_trigger->width;
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not_cell->parameters["\\A_SIGNED"] = 0;
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not_cell->setPort("\\A", all_conditions);
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not_cell->setPort("\\Y", w_trigger);
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miter_module->fixup_ports();
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if (flag_flatten) {
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log_push();
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Pass::call_on_module(design, miter_module, "flatten; opt_expr -keepdc -undriven;;");
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log_pop();
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}
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}
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void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_make_outputs = false;
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bool flag_flatten = false;
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log_header(design, "Executing MITER pass (creating miter circuit).\n");
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size_t argidx;
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for (argidx = 2; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-make_outputs") {
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flag_make_outputs = true;
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continue;
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}
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if (args[argidx] == "-flatten") {
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flag_flatten = true;
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continue;
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}
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break;
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}
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if ((argidx+1 != args.size() && argidx+2 != args.size()) || args[argidx].substr(0, 1) == "-")
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that->cmd_error(args, argidx, "command argument error");
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IdString module_name = RTLIL::escape_id(args[argidx++]);
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IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : "";
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if (design->modules_.count(module_name) == 0)
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log_cmd_error("Can't find module %s!\n", module_name.c_str());
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if (!miter_name.empty() && design->modules_.count(miter_name) != 0)
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log_cmd_error("There is already a module %s!\n", miter_name.c_str());
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Module *module = design->module(module_name);
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if (!miter_name.empty()) {
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module = module->clone();
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module->name = miter_name;
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design->add(module);
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}
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if (!flag_make_outputs)
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for (auto wire : module->wires())
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wire->port_output = false;
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Wire *trigger = module->addWire("\\trigger");
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trigger->port_output = true;
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module->fixup_ports();
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if (flag_flatten) {
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log_push();
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Pass::call_on_module(design, module, "flatten;;");
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log_pop();
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}
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SigSpec assert_signals, assume_signals;
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vector<Cell*> cell_list = module->cells();
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for (auto cell : cell_list)
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{
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if (!cell->type.in("$assert", "$assume"))
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continue;
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SigBit is_active = module->Nex(NEW_ID, cell->getPort("\\A"), State::S1);
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SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort("\\EN"), State::S1);
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if (cell->type == "$assert") {
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assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
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} else {
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assume_signals.append(module->And(NEW_ID, is_active, is_enabled));
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}
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module->remove(cell);
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}
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if (assume_signals.empty())
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{
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module->addReduceOr(NEW_ID, assert_signals, trigger);
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}
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else
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{
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Wire *assume_q = module->addWire(NEW_ID);
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assume_q->attributes["\\init"] = State::S0;
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assume_signals.append(assume_q);
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SigSpec assume_nok = module->ReduceOr(NEW_ID, assume_signals);
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SigSpec assume_ok = module->Not(NEW_ID, assume_nok);
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module->addFf(NEW_ID, assume_nok, assume_q);
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SigSpec assert_fail = module->ReduceOr(NEW_ID, assert_signals);
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module->addAnd(NEW_ID, assert_fail, assume_ok, trigger);
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}
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if (flag_flatten) {
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log_push();
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Pass::call_on_module(design, module, "opt_expr -keepdc -undriven;;");
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log_pop();
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}
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}
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struct MiterPass : public Pass {
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MiterPass() : Pass("miter", "automatically create a miter circuit") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" miter -equiv [options] gold_name gate_name miter_name\n");
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log("\n");
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log("Creates a miter circuit for equivalence checking. The gold- and gate- modules\n");
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log("must have the same interfaces. The miter circuit will have all inputs of the\n");
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log("two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'\n");
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log("output that goes high if an output mismatch between the two source modules is\n");
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log("detected.\n");
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log("\n");
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log(" -ignore_gold_x\n");
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log(" a undef (x) bit in the gold module output will match any value in\n");
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log(" the gate module output.\n");
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log("\n");
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log(" -make_outputs\n");
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log(" also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs\n");
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log(" on the miter circuit.\n");
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log("\n");
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log(" -make_outcmp\n");
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log(" also create a cmp_* output for each gold/gate output pair.\n");
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log("\n");
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log(" -make_assert\n");
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log(" also create an 'assert' cell that checks if trigger is always low.\n");
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log("\n");
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log(" -flatten\n");
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log(" call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.\n");
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log("\n");
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log("\n");
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log(" miter -assert [options] module [miter_name]\n");
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log("\n");
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log("Creates a miter circuit for property checking. All input ports are kept,\n");
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log("output ports are discarded. An additional output 'trigger' is created that\n");
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log("goes high when an assert is violated. Without a miter_name, the existing\n");
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log("module is modified.\n");
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log("\n");
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log(" -make_outputs\n");
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log(" keep module output ports.\n");
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log("\n");
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log(" -flatten\n");
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log(" call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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if (args.size() > 1 && args[1] == "-equiv") {
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create_miter_equiv(this, args, design);
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return;
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}
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if (args.size() > 1 && args[1] == "-assert") {
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create_miter_assert(this, args, design);
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return;
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}
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log_cmd_error("Missing mode parameter!\n");
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}
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} MiterPass;
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PRIVATE_NAMESPACE_END
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