399 lines
14 KiB
C++
399 lines
14 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <stdlib.h>
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#include <stdio.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
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{
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RTLIL::SigSpec lvalue;
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for (auto sync : proc->syncs)
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for (auto &action : sync->actions)
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if (action.first.size() > 0) {
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lvalue = action.first;
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lvalue.sort_and_unify();
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break;
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}
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for (auto sync : proc->syncs) {
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RTLIL::SigSpec this_lvalue;
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for (auto &action : sync->actions)
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this_lvalue.append(action.first);
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this_lvalue.sort_and_unify();
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RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);
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if (common_sig.size() > 0)
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lvalue = common_sig;
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}
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return lvalue;
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}
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void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
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std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
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{
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RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
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RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
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for (auto &it : async_rules)
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{
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RTLIL::SigSpec sync_value = it.first;
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RTLIL::SigSpec sync_value_inv;
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RTLIL::SigSpec sync_high_signals;
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RTLIL::SigSpec sync_low_signals;
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for (auto &it2 : it.second)
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if (it2->type == RTLIL::SyncType::ST0)
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sync_low_signals.append(it2->signal);
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else if (it2->type == RTLIL::SyncType::ST1)
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sync_high_signals.append(it2->signal);
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else
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log_abort();
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if (sync_low_signals.size() > 1) {
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RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->setPort("\\A", sync_low_signals);
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cell->setPort("\\Y", sync_low_signals = mod->addWire(NEW_ID));
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}
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if (sync_low_signals.size() > 0) {
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RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not");
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->setPort("\\A", sync_low_signals);
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cell->setPort("\\Y", mod->addWire(NEW_ID));
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sync_high_signals.append(cell->getPort("\\Y"));
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}
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if (sync_high_signals.size() > 1) {
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RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or");
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->setPort("\\A", sync_high_signals);
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cell->setPort("\\Y", sync_high_signals = mod->addWire(NEW_ID));
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}
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RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not");
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inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size());
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inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size());
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inv_cell->setPort("\\A", sync_value);
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inv_cell->setPort("\\Y", sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
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RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux");
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mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
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mux_set_cell->setPort("\\A", sig_sr_set);
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mux_set_cell->setPort("\\B", sync_value);
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mux_set_cell->setPort("\\S", sync_high_signals);
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mux_set_cell->setPort("\\Y", sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
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RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux");
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mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
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mux_clr_cell->setPort("\\A", sig_sr_clr);
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mux_clr_cell->setPort("\\B", sync_value_inv);
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mux_clr_cell->setPort("\\S", sync_high_signals);
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mux_clr_cell->setPort("\\Y", sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
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}
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
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cell->attributes = proc->attributes;
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cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size());
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
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cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
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cell->setPort("\\D", sig_d);
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cell->setPort("\\Q", sig_q);
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cell->setPort("\\CLK", clk);
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cell->setPort("\\SET", sig_sr_set);
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cell->setPort("\\CLR", sig_sr_clr);
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log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
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cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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}
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void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
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bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
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{
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
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RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
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RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
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RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not");
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inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size());
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inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size());
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inv_set->setPort("\\A", sig_set);
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inv_set->setPort("\\Y", sig_set_inv);
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RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux");
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mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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mux_sr_set->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
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mux_sr_set->setPort(set_polarity ? "\\B" : "\\A", sig_set);
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mux_sr_set->setPort("\\Y", sig_sr_set);
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mux_sr_set->setPort("\\S", set);
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RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux");
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mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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mux_sr_clr->setPort(set_polarity ? "\\A" : "\\B", RTLIL::Const(0, sig_in.size()));
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mux_sr_clr->setPort(set_polarity ? "\\B" : "\\A", sig_set_inv);
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mux_sr_clr->setPort("\\Y", sig_sr_clr);
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mux_sr_clr->setPort("\\S", set);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr");
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cell->attributes = proc->attributes;
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cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1);
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cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
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cell->setPort("\\D", sig_in);
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cell->setPort("\\Q", sig_out);
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cell->setPort("\\CLK", clk);
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cell->setPort("\\SET", sig_sr_set);
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cell->setPort("\\CLR", sig_sr_clr);
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log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
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clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
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}
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void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
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bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
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{
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std::stringstream sstr;
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sstr << "$procdff$" << (autoidx++);
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RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? "$ff" : arst ? "$adff" : "$dff");
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cell->attributes = proc->attributes;
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cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size());
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if (arst) {
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cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1);
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cell->parameters["\\ARST_VALUE"] = val_rst;
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}
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if (!clk.empty()) {
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cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1);
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}
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cell->setPort("\\D", sig_in);
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cell->setPort("\\Q", sig_out);
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if (arst)
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cell->setPort("\\ARST", *arst);
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if (!clk.empty())
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cell->setPort("\\CLK", clk);
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if (!clk.empty())
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log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
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else
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log(" created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
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if (arst)
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log(" and %s level reset", arst_polarity ? "positive" : "negative");
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log(".\n");
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}
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void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
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{
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while (1)
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{
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RTLIL::SigSpec sig = find_any_lvalue(proc);
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bool free_sync_level = false;
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if (sig.size() == 0)
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break;
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log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
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mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
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RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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RTLIL::SyncRule *sync_level = NULL;
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RTLIL::SyncRule *sync_edge = NULL;
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RTLIL::SyncRule *sync_always = NULL;
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bool global_clock = false;
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std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> many_async_rules;
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for (auto sync : proc->syncs)
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for (auto &action : sync->actions)
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{
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if (action.first.extract(sig).size() == 0)
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continue;
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if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
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if (sync_level != NULL && sync_level != sync) {
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// log_error("Multiple level sensitive events found for this signal!\n");
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many_async_rules[rstval].insert(sync_level);
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rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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}
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rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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sig.replace(action.first, action.second, &rstval);
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sync_level = sync;
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}
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else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
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if (sync_edge != NULL && sync_edge != sync)
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log_error("Multiple edge sensitive events found for this signal!\n");
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sig.replace(action.first, action.second, &insig);
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sync_edge = sync;
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}
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else if (sync->type == RTLIL::SyncType::STa) {
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if (sync_always != NULL && sync_always != sync)
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log_error("Multiple always events found for this signal!\n");
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sig.replace(action.first, action.second, &insig);
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sync_always = sync;
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}
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else if (sync->type == RTLIL::SyncType::STg) {
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sig.replace(action.first, action.second, &insig);
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global_clock = true;
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}
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else {
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log_error("Event with any-edge sensitivity found for this signal!\n");
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}
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action.first.remove2(sig, &action.second);
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}
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if (many_async_rules.size() > 0)
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{
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many_async_rules[rstval].insert(sync_level);
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if (many_async_rules.size() == 1)
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{
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sync_level = new RTLIL::SyncRule;
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sync_level->type = RTLIL::SyncType::ST1;
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sync_level->signal = mod->addWire(NEW_ID);
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sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));
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free_sync_level = true;
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RTLIL::SigSpec inputs, compare;
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for (auto &it : many_async_rules[rstval]) {
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inputs.append(it->signal);
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compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
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}
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log_assert(inputs.size() == compare.size());
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RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
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cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
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cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1);
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cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size());
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cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size());
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cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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cell->setPort("\\A", inputs);
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cell->setPort("\\B", compare);
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cell->setPort("\\Y", sync_level->signal);
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many_async_rules.clear();
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}
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else
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{
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rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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sync_level = NULL;
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}
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}
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ce.assign_map.apply(insig);
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ce.assign_map.apply(rstval);
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ce.assign_map.apply(sig);
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if (rstval == sig) {
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rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
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sync_level = NULL;
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}
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if (sync_always) {
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if (sync_edge || sync_level || many_async_rules.size() > 0)
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log_error("Mixed always event with edge and/or level sensitive events!\n");
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log(" created direct connection (no actual register cell created).\n");
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mod->connect(RTLIL::SigSig(sig, insig));
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continue;
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}
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if (!sync_edge && !global_clock)
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log_error("Missing edge-sensitive event for this signal!\n");
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if (many_async_rules.size() > 0)
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{
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log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
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gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
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}
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else if (!rstval.is_fully_const() && !ce.eval(rstval))
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{
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log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
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gen_dffsr(mod, insig, rstval, sig,
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sync_edge->type == RTLIL::SyncType::STp,
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sync_level && sync_level->type == RTLIL::SyncType::ST1,
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sync_edge->signal, sync_level->signal, proc);
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}
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else
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gen_dff(mod, insig, rstval.as_const(), sig,
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sync_edge && sync_edge->type == RTLIL::SyncType::STp,
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sync_level && sync_level->type == RTLIL::SyncType::ST1,
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sync_edge ? sync_edge->signal : SigSpec(),
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sync_level ? &sync_level->signal : NULL, proc);
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if (free_sync_level)
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delete sync_level;
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}
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}
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struct ProcDffPass : public Pass {
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ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" proc_dff [selection]\n");
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log("\n");
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log("This pass identifies flip-flops in the processes and converts them to\n");
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log("d-type flip-flop cells.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
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extra_args(args, 1, design);
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for (auto mod : design->modules())
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if (design->selected(mod)) {
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ConstEval ce(mod);
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for (auto &proc_it : mod->processes)
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if (design->selected(mod, proc_it.second))
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proc_dff(mod, proc_it.second, ce);
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}
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}
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} ProcDffPass;
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PRIVATE_NAMESPACE_END
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