290 lines
8.5 KiB
C++
290 lines
8.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "fsmdata.h"
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#include <string.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct FsmExpand
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{
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RTLIL::Module *module;
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RTLIL::Cell *fsm_cell;
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bool full_mode;
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SigMap assign_map;
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SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
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CellTypes ct;
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
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std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
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bool already_optimized;
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int limit_transitions;
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bool is_cell_merge_candidate(RTLIL::Cell *cell)
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{
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if (full_mode || cell->type == "$_MUX_")
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return true;
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if (cell->type == "$mux" || cell->type == "$pmux")
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if (cell->getPort("\\A").size() < 2)
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return true;
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RTLIL::SigSpec new_signals;
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if (cell->hasPort("\\A"))
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new_signals.append(assign_map(cell->getPort("\\A")));
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if (cell->hasPort("\\B"))
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new_signals.append(assign_map(cell->getPort("\\B")));
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if (cell->hasPort("\\S"))
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new_signals.append(assign_map(cell->getPort("\\S")));
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if (cell->hasPort("\\Y"))
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new_signals.append(assign_map(cell->getPort("\\Y")));
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new_signals.sort_and_unify();
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new_signals.remove_const();
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
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if (new_signals.size() > 3)
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return false;
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return true;
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}
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void create_current_set()
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{
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std::vector<RTLIL::Cell*> cell_list;
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for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
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cell_list.push_back(c);
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for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
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cell_list.push_back(c);
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current_set.clear();
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for (auto c : cell_list)
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{
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if (merged_set.count(c) > 0 || current_set.count(c) > 0 || no_candidate_set.count(c) > 0)
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continue;
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for (auto &p : c->connections()) {
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if (p.first != "\\A" && p.first != "\\B" && p.first != "\\S" && p.first != "\\Y")
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goto next_cell;
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}
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if (!is_cell_merge_candidate(c)) {
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no_candidate_set.insert(c);
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continue;
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}
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current_set.insert(c);
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next_cell:;
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}
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}
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void optimze_as_needed()
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{
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if (already_optimized)
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return;
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int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
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if (trans_num > limit_transitions)
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{
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log(" grown transition table to %d entries -> optimize.\n", trans_num);
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FsmData::optimize_fsm(fsm_cell, module);
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already_optimized = true;
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trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
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log(" transition table size after optimizaton: %d\n", trans_num);
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limit_transitions = 16 * trans_num;
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}
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}
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void merge_cell_into_fsm(RTLIL::Cell *cell)
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{
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optimze_as_needed();
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log(" merging %s cell %s.\n", cell->type.c_str(), cell->name.c_str());
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merged_set.insert(cell);
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already_optimized = false;
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RTLIL::SigSpec input_sig, output_sig;
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for (auto &p : cell->connections())
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if (ct.cell_output(cell->type, p.first))
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output_sig.append(assign_map(p.second));
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else
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input_sig.append(assign_map(p.second));
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input_sig.sort_and_unify();
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input_sig.remove_const();
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std::vector<RTLIL::Const> truth_tab;
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for (int i = 0; i < (1 << input_sig.size()); i++) {
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RTLIL::Const in_val(i, input_sig.size());
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RTLIL::SigSpec A, B, S;
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if (cell->hasPort("\\A"))
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A = assign_map(cell->getPort("\\A"));
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if (cell->hasPort("\\B"))
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B = assign_map(cell->getPort("\\B"));
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if (cell->hasPort("\\S"))
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S = assign_map(cell->getPort("\\S"));
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A.replace(input_sig, RTLIL::SigSpec(in_val));
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B.replace(input_sig, RTLIL::SigSpec(in_val));
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S.replace(input_sig, RTLIL::SigSpec(in_val));
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log_assert(A.is_fully_const());
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log_assert(B.is_fully_const());
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log_assert(S.is_fully_const());
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truth_tab.push_back(ct.eval(cell, A.as_const(), B.as_const(), S.as_const()));
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}
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FsmData fsm_data;
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fsm_data.copy_from_cell(fsm_cell);
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fsm_data.num_inputs += input_sig.size();
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RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
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new_ctrl_in.append(input_sig);
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fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
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fsm_data.num_outputs += output_sig.size();
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RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
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new_ctrl_out.append(output_sig);
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fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
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std::vector<FsmData::transition_t> new_transition_table;
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for (auto &tr : fsm_data.transition_table) {
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for (int i = 0; i < (1 << input_sig.size()); i++) {
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FsmData::transition_t new_tr = tr;
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RTLIL::Const in_val(i, input_sig.size());
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RTLIL::Const out_val = truth_tab[i];
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RTLIL::SigSpec ctrl_in = new_tr.ctrl_in;
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RTLIL::SigSpec ctrl_out = new_tr.ctrl_out;
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ctrl_in.append(in_val);
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ctrl_out.append(out_val);
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new_tr.ctrl_in = ctrl_in.as_const();
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new_tr.ctrl_out = ctrl_out.as_const();
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new_transition_table.push_back(new_tr);
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}
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}
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fsm_data.transition_table.swap(new_transition_table);
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new_transition_table.clear();
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fsm_data.copy_to_cell(fsm_cell);
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}
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FsmExpand(RTLIL::Cell *cell, RTLIL::Design *design, RTLIL::Module *mod, bool full)
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{
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module = mod;
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fsm_cell = cell;
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full_mode = full;
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assign_map.set(module);
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ct.setup_internals();
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ct.setup_stdcells();
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *c = cell_it.second;
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if (ct.cell_known(c->type) && design->selected(mod, c))
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for (auto &p : c->connections()) {
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if (ct.cell_output(c->type, p.first))
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sig2driver.insert(assign_map(p.second), c);
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else
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sig2user.insert(assign_map(p.second), c);
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}
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}
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}
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void execute()
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{
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log("\n");
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log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
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already_optimized = false;
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limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int();
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for (create_current_set(); current_set.size() > 0; create_current_set()) {
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for (auto c : current_set)
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merge_cell_into_fsm(c);
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}
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for (auto c : merged_set)
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module->remove(c);
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if (merged_set.size() > 0 && !already_optimized)
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FsmData::optimize_fsm(fsm_cell, module);
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log(" merged %d cells into FSM.\n", GetSize(merged_set));
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}
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};
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struct FsmExpandPass : public Pass {
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FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" fsm_expand [-full] [selection]\n");
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log("\n");
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log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
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log("state machine. This pass can be used to merge additional auxiliary gates into\n");
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log("the finite state machine.\n");
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log("\n");
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log("By default, fsm_expand is still a bit conservative regarding merging larger\n");
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log("word-wide cells. Call with -full to consider all cells for merging.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool full_mode = false;
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log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-full") {
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full_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules_) {
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if (!design->selected(mod_it.second))
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continue;
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std::vector<RTLIL::Cell*> fsm_cells;
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for (auto &cell_it : mod_it.second->cells_)
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
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fsm_cells.push_back(cell_it.second);
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for (auto c : fsm_cells) {
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FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
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fsm_expand.execute();
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}
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}
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}
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} FsmExpandPass;
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PRIVATE_NAMESPACE_END
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