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OpenFPGA
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OpenFPGA/vpr7_x2p/vpr/VerilogNetlists
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Aur??Lien ALACCHI 8ac566ecc0 Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
..
ff.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
ff_tb.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
io.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
lb_tb.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
lut6.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
mux_tb.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00
sram.v Add timing and initialization for simulation 2018-12-04 17:32:09 -07:00
sram_tb.v rename customized vpr7 to vpr7 XML to Production 2018-09-17 23:10:45 -06:00