816 lines
38 KiB
XML
816 lines
38 KiB
XML
<!--
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Architecture based off Stratix IV
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Use closest ifar architecture: K06 N10 45nm fc 0.15 area-delay optimized, scale to 40 nm using linear scaling
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n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml
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- because documentation sparser for soft logic (delays not in QUIP), harder to track down, not worth our time considering the level of accuracy is approximate
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- delays multiplied by 40/45 to normalize for process difference between stratix 4 and 45 nm technology (called full scaling)
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Use delay numbers off Altera device handbook:
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http://www.altera.com/literature/hb/stratix-iv/stx4_5v1.pdf
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http://www.altera.com/literature/hb/stratix-iv/stx4_siv51004.pdf
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http://www.altera.com/literature/hb/stratix-iv/stx4_siv51003.pdf
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multipliers at 600 MHz, no detail on 9x9 vs 36x36
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- datasheets unclear
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- claims 4 18x18 independant multipliers, following test indicates that this is not the case:
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created 4 18x18 mulitpliers, logiclocked them to a single DSP block, compile
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result - 2 18x18 multipliers got packed together, the other 2 got ejected out of the logiclock region without error
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conclusion - just take the 600 MHz as is, and Quartus II logiclock hasn't fixed the bug that I've seen it do to registers when I worked at Altera (ie. eject without warning)
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NOTE: Area numbers for hard blocks unknown!
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-->
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<architecture>
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<!-- ODIN II specific config -->
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<models>
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<model name="multiply">
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<input_ports>
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<port name="a"/>
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<port name="b"/>
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</input_ports>
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<output_ports>
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<port name="out"/>
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</output_ports>
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</model>
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<model name="single_port_ram">
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<input_ports>
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<port name="we"/> <!-- control -->
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<port name="addr"/> <!-- address lines -->
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<port name="data"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
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</input_ports>
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<output_ports>
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<port name="out"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
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</output_ports>
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</model>
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<model name="dual_port_ram">
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<input_ports>
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<port name="we1"/> <!-- write enable -->
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<port name="we2"/> <!-- write enable -->
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<port name="addr1"/> <!-- address lines -->
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<port name="addr2"/> <!-- address lines -->
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<port name="data1"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="data2"/> <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
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<port name="clk" is_clock="1"/> <!-- memories are often clocked -->
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</input_ports>
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<output_ports>
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<port name="out1"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
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<port name="out2"/> <!-- output can be broken down into smaller bit widths minimum size 1 -->
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</output_ports>
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</model>
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<!-- fake carry-chain example -->
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<model name="alm">
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<input_ports>
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<port name="in"/>
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<port name="cin"/>
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</input_ports>
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<output_ports>
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<port name="out"/>
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<port name="cout"/>
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</output_ports>
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</model>
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<model name="adder">
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<input_ports>
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<port name="a"/>
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<port name="b"/>
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<port name="cin"/>
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</input_ports>
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<output_ports>
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<port name="cout"/>
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<port name="sumout"/>
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</output_ports>
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</model>
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<!--
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<model name="sub">
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<input_ports>
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<port name="a"/>
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<port name="b"/>
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<port name="cin"/>
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</input_ports>
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<output_ports>
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<port name="cout"/>
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<port name="sumout"/>
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</output_ports>
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</model>
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-->
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</models>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin (area optimized for N8-K6-L4 -->
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<layout auto="1.0"/>
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<device>
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<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000" ipin_mux_trans_size="1.222260"/>
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<timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="7.247000e-11"/>
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<area grid_logic_tile_area="14813.392"/>
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<chan_width_distr>
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<io width="1.000000"/>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.837e-11" mux_trans_size="2.630740" buf_size="27.645901"/>
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</switchlist>
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<segmentlist>
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<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
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<pb_type name="io" capacity="8">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs -->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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<gridlocations>
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<loc type="perimeter" priority="10"/>
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</gridlocations>
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</pb_type>
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<pb_type name="clb">
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<input name="I" num_pins="33" equivalent="true"/>
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<output name="O" num_pins="10" equivalent="false"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe basic logic element, with ifar delay numbers -->
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<pb_type name="ble" num_pb="10">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<pb_type name="soft_logic" num_pb="1">
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<input name="in" num_pins="6"/>
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<output name="out" num_pins="1"/>
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<mode name="n1_lut6">
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<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="6" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
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2.690e-10
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2.690e-10
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2.690e-10
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2.690e-10
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2.690e-10
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2.690e-10
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</delay_matrix>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="soft_logic.in[5:0]" output="lut6[0:0].in[5:0]"/>
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<direct name="direct2" input="lut6[0:0].out" output="soft_logic.out[0:0]">
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<!-- CAD related parameters -->
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<!-- Advanced "power-user" options: Describe connections that belong to forced pack blocks to give hints to the packer on what blocks to keep together
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Assumes pattern nets must be single-fanout
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-->
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<pack_pattern name="ble" in_port="lut6[0:0].out" out_port="soft_logic.out[0:0]"/>
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<!-- CAD related parameters -->
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</direct>
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</interconnect>
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</mode>
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</pb_type>
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="2.448e-10" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="7.732e-11" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<!-- Two ff, make ff available to only corresponding luts -->
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<direct name="direct1" input="ble.in" output="soft_logic.in"/>
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<direct name="direct2" input="soft_logic.out" output="ff.D">
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<pack_pattern name="ble" in_port="soft_logic.out" out_port="ff.D"/>
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</direct>
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<direct name="direct4" input="ble.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q soft_logic.out" output="ble.out"/>
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</interconnect>
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</pb_type>
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<interconnect>
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<complete name="crossbar" input="clb.I ble[9:0].out" output="ble[9:0].in">
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<delay_constant max="8.044000e-11" in_port="clb.I" out_port="ble[9:0].in" />
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<delay_constant max="7.354000e-11" in_port="ble[9:0].out" out_port="ble[9:0].in" />
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</complete>
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<complete name="clks" input="clb.clk" output="ble[9:0].clk">
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</complete>
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<direct name="clbouts" input="ble[9:0].out" output="clb.O">
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</direct>
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</interconnect>
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<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="fill" priority="1"/>
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</gridlocations>
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</pb_type>
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<!-- This is the 36*36 uniform mult -->
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<pb_type name="mult_36" height="4">
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<input name="a" num_pins="36"/>
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<input name="b" num_pins="36"/>
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<output name="out" num_pins="72"/>
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<mode name="two_divisible_mult_18x18">
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<pb_type name="divisible_mult_18x18" num_pb="2">
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<input name="a" num_pins="18"/>
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<input name="b" num_pins="18"/>
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<output name="out" num_pins="36"/>
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<mode name="two_mult_9x9">
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<pb_type name="mult_9x9_slice" num_pb="2">
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<input name="A_cfg" num_pins="9"/>
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<input name="B_cfg" num_pins="9"/>
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<output name="OUT_cfg" num_pins="18"/>
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<pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
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<input name="a" num_pins="9"/>
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<input name="b" num_pins="9"/>
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<output name="out" num_pins="18"/>
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<delay_constant max="1.667e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
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<delay_constant max="1.667e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
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</direct>
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<direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
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</direct>
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<direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
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</direct>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
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</direct>
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<direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
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</direct>
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<direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
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</direct>
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</interconnect>
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</mode>
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<mode name="mult_18x18">
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<pb_type name="mult_18x18_slice" num_pb="1">
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<input name="A_cfg" num_pins="18"/>
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<input name="B_cfg" num_pins="18"/>
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<output name="OUT_cfg" num_pins="36"/>
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<pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1" >
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<input name="a" num_pins="18"/>
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<input name="b" num_pins="18"/>
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<output name="out" num_pins="36"/>
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<delay_constant max="1.667e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
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<delay_constant max="1.667e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
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</direct>
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<direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
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</direct>
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<direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
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</direct>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
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</direct>
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<direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
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</direct>
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<direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
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</direct>
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</interconnect>
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</mode>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
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</direct>
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<direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
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</direct>
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<direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
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</direct>
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</interconnect>
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</mode>
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<mode name="mult_36x36">
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<pb_type name="mult_36x36_slice" num_pb="1">
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<input name="A_cfg" num_pins="36"/>
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<input name="B_cfg" num_pins="36"/>
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<output name="OUT_cfg" num_pins="72"/>
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<pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
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<input name="a" num_pins="36"/>
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<input name="b" num_pins="36"/>
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<output name="out" num_pins="72"/>
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<delay_constant max="1.667e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
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<delay_constant max="1.667e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
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</direct>
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<direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
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</direct>
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<direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
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</direct>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
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</direct>
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<direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
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</direct>
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<direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
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</direct>
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</interconnect>
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</mode>
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<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
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<pinlocations pattern="spread"/>
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<gridlocations>
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<loc type="col" start="4" repeat="8" priority="2"/>
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</gridlocations>
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</pb_type>
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<!-- Memory based off Stratix IV 144K memory. Setup time set to match flip-flop setup time at 45 nm. Clock to q based off 144K max MHz -->
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<pb_type name="memory" height="6">
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<input name="addr1" num_pins="17"/>
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<input name="addr2" num_pins="17"/>
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<input name="data" num_pins="72"/>
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<input name="we1" num_pins="1"/>
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<input name="we2" num_pins="1"/>
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<output name="out" num_pins="72"/>
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<clock name="clk" num_pins="1"/>
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<mode name="mem_2048x72_sp">
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<pb_type name="mem_2048x72_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
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<input name="addr" num_pins="11" port_class="address"/>
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<input name="data" num_pins="72" port_class="data_in"/>
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<input name="we" num_pins="1" port_class="write_en"/>
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<output name="out" num_pins="72" port_class="data_out"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="2.448e-10" port="mem_2048x72_sp.addr" clock="clk"/>
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<T_setup value="2.448e-10" port="mem_2048x72_sp.data" clock="clk"/>
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<T_setup value="2.448e-10" port="mem_2048x72_sp.we" clock="clk"/>
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<T_clock_to_Q max="1.852e-9" port="mem_2048x72_sp.out" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="address1" input="memory.addr1[10:0]" output="mem_2048x72_sp.addr">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[71:0]" output="mem_2048x72_sp.data">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_2048x72_sp.we">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_2048x72_sp.out" output="memory.out[71:0]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_2048x72_sp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="mem_4096x36_dp">
|
|
<pb_type name="mem_4096x36_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
|
<input name="addr1" num_pins="12" port_class="address1"/>
|
|
<input name="addr2" num_pins="12" port_class="address2"/>
|
|
<input name="data1" num_pins="36" port_class="data_in1"/>
|
|
<input name="data2" num_pins="36" port_class="data_in2"/>
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
|
<output name="out1" num_pins="36" port_class="data_out1"/>
|
|
<output name="out2" num_pins="36" port_class="data_out2"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.addr1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.data1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.we1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.addr2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.data2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_dp.we2" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_dp.out1" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_dp.out2" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x36_dp.addr1">
|
|
</direct>
|
|
<direct name="address2" input="memory.addr2[11:0]" output="mem_4096x36_dp.addr2">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[35:0]" output="mem_4096x36_dp.data1">
|
|
</direct>
|
|
<direct name="data2" input="memory.data[71:36]" output="mem_4096x36_dp.data2">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_4096x36_dp.we1">
|
|
</direct>
|
|
<direct name="writeen2" input="memory.we2" output="mem_4096x36_dp.we2">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_4096x36_dp.out1" output="memory.out[35:0]">
|
|
</direct>
|
|
<direct name="dataout2" input="mem_4096x36_dp.out2" output="memory.out[71:36]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_4096x36_dp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<mode name="mem_4096x36_sp">
|
|
<pb_type name="mem_4096x36_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
|
<input name="addr" num_pins="12" port_class="address"/>
|
|
<input name="data" num_pins="36" port_class="data_in"/>
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
|
<output name="out" num_pins="36" port_class="data_out"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_sp.addr" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_sp.data" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_4096x36_sp.we" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_4096x36_sp.out" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[11:0]" output="mem_4096x36_sp.addr">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[35:0]" output="mem_4096x36_sp.data">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_4096x36_sp.we">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_4096x36_sp.out" output="memory.out[35:0]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_4096x36_sp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="mem_9182x18_dp">
|
|
<pb_type name="mem_9182x18_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
|
<input name="addr1" num_pins="13" port_class="address1"/>
|
|
<input name="addr2" num_pins="13" port_class="address2"/>
|
|
<input name="data1" num_pins="18" port_class="data_in1"/>
|
|
<input name="data2" num_pins="18" port_class="data_in2"/>
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
|
<output name="out1" num_pins="18" port_class="data_out1"/>
|
|
<output name="out2" num_pins="18" port_class="data_out2"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.addr1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.data1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.we1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.addr2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.data2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_dp.we2" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_dp.out1" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_dp.out2" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[12:0]" output="mem_9182x18_dp.addr1">
|
|
</direct>
|
|
<direct name="address2" input="memory.addr2[12:0]" output="mem_9182x18_dp.addr2">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[17:0]" output="mem_9182x18_dp.data1">
|
|
</direct>
|
|
<direct name="data2" input="memory.data[35:18]" output="mem_9182x18_dp.data2">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_9182x18_dp.we1">
|
|
</direct>
|
|
<direct name="writeen2" input="memory.we2" output="mem_9182x18_dp.we2">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_9182x18_dp.out1" output="memory.out[17:0]">
|
|
</direct>
|
|
<direct name="dataout2" input="mem_9182x18_dp.out2" output="memory.out[35:18]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_9182x18_dp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<mode name="mem_9182x18_sp">
|
|
<pb_type name="mem_9182x18_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
|
<input name="addr" num_pins="13" port_class="address"/>
|
|
<input name="data" num_pins="18" port_class="data_in"/>
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
|
<output name="out" num_pins="18" port_class="data_out"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_sp.addr" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_sp.data" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_9182x18_sp.we" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_9182x18_sp.out" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[12:0]" output="mem_9182x18_sp.addr">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[17:0]" output="mem_9182x18_sp.data">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_9182x18_sp.we">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_9182x18_sp.out" output="memory.out[17:0]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_9182x18_sp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
<mode name="mem_18194x9_dp">
|
|
<pb_type name="mem_18194x9_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
|
|
<input name="addr1" num_pins="14" port_class="address1"/>
|
|
<input name="addr2" num_pins="14" port_class="address2"/>
|
|
<input name="data1" num_pins="9" port_class="data_in1"/>
|
|
<input name="data2" num_pins="9" port_class="data_in2"/>
|
|
<input name="we1" num_pins="1" port_class="write_en1"/>
|
|
<input name="we2" num_pins="1" port_class="write_en2"/>
|
|
<output name="out1" num_pins="9" port_class="data_out1"/>
|
|
<output name="out2" num_pins="9" port_class="data_out2"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.addr1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.data1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.we1" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.addr2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.data2" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_dp.we2" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_dp.out1" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_dp.out2" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[13:0]" output="mem_18194x9_dp.addr1">
|
|
</direct>
|
|
<direct name="address2" input="memory.addr2[13:0]" output="mem_18194x9_dp.addr2">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[8:0]" output="mem_18194x9_dp.data1">
|
|
</direct>
|
|
<direct name="data2" input="memory.data[17:9]" output="mem_18194x9_dp.data2">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_18194x9_dp.we1">
|
|
</direct>
|
|
<direct name="writeen2" input="memory.we2" output="mem_18194x9_dp.we2">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_18194x9_dp.out1" output="memory.out[8:0]">
|
|
</direct>
|
|
<direct name="dataout2" input="mem_18194x9_dp.out2" output="memory.out[17:9]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_18194x9_dp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<mode name="mem_18194x9_sp">
|
|
<pb_type name="mem_18194x9_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
|
|
<input name="addr" num_pins="14" port_class="address"/>
|
|
<input name="data" num_pins="9" port_class="data_in"/>
|
|
<input name="we" num_pins="1" port_class="write_en"/>
|
|
<output name="out" num_pins="9" port_class="data_out"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_sp.addr" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_sp.data" clock="clk"/>
|
|
<T_setup value="2.448e-10" port="mem_18194x9_sp.we" clock="clk"/>
|
|
<T_clock_to_Q max="1.852e-9" port="mem_18194x9_sp.out" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<direct name="address1" input="memory.addr1[13:0]" output="mem_18194x9_sp.addr">
|
|
</direct>
|
|
<direct name="data1" input="memory.data[8:0]" output="mem_18194x9_sp.data">
|
|
</direct>
|
|
<direct name="writeen1" input="memory.we1" output="mem_18194x9_sp.we">
|
|
</direct>
|
|
<direct name="dataout1" input="mem_18194x9_sp.out" output="memory.out[8:0]">
|
|
</direct>
|
|
<direct name="clk" input="memory.clk" output="mem_18194x9_sp.clk">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
|
|
<pinlocations pattern="spread"/>
|
|
<gridlocations>
|
|
<loc type="col" start="2" repeat="8" priority="2"/>
|
|
</gridlocations>
|
|
</pb_type>
|
|
|
|
|
|
|
|
<!-- fake carry-chain example -->
|
|
<pb_type name="carry_chain_example">
|
|
<input name="I" num_pins="15" equivalent="true"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="O" num_pins="4" equivalent="false"/>
|
|
<output name="cout" num_pins="1" equivalent="false"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
|
|
<!-- Describe basic logic element, with ifar delay numbers -->
|
|
<pb_type name="ble" num_pb="4">
|
|
<input name="in" num_pins="6"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="out" num_pins="1"/>
|
|
<output name="cout" num_pins="1"/>
|
|
<clock name="clk" num_pins="1"/>
|
|
<pb_type name="alm" blif_model=".subckt alm" num_pb="1">
|
|
<input name="in" num_pins="6"/>
|
|
<input name="cin" num_pins="1" chain="carry_chain_alm"/>
|
|
<output name="out" num_pins="1"/>
|
|
<output name="cout" num_pins="1" chain="carry_chain_alm"/>
|
|
|
|
|
|
<!-- LUT timing using delay matrix -->
|
|
<delay_matrix type="max" in_port="alm.in" out_port="alm.out">
|
|
2.690e-10
|
|
2.690e-10
|
|
2.690e-10
|
|
2.690e-10
|
|
2.690e-10
|
|
2.690e-10
|
|
</delay_matrix>
|
|
|
|
<!-- LUT timing using delay matrix -->
|
|
<delay_matrix type="max" in_port="alm.cin" out_port="alm.out">
|
|
2.690e-10
|
|
</delay_matrix>
|
|
|
|
<!-- LUT timing using delay matrix -->
|
|
<delay_matrix type="max" in_port="alm.cin" out_port="alm.cout">
|
|
1.690e-10
|
|
</delay_matrix>
|
|
</pb_type>
|
|
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
|
|
<input name="D" num_pins="1" port_class="D"/>
|
|
<output name="Q" num_pins="1" port_class="Q"/>
|
|
<clock name="clk" num_pins="1" port_class="clock"/>
|
|
<T_setup value="2.448e-10" port="ff.D" clock="clk"/>
|
|
<T_clock_to_Q max="7.732e-11" port="ff.Q" clock="clk"/>
|
|
</pb_type>
|
|
<interconnect>
|
|
<!-- Two ff, make ff available to only corresponding luts -->
|
|
<complete name="complete1" input="ble.in" output="alm.in ff.D"/>
|
|
<direct name="direct4" input="ble.clk" output="ff.clk"/>
|
|
<direct name="direct5" input="ble.cin" output="alm.cin"/>
|
|
<direct name="direct6" input="alm.cout" output="ble.cout"/>
|
|
<mux name="mux1" input="ff.Q alm.out" output="ble.out"/>
|
|
</interconnect>
|
|
</pb_type>
|
|
<interconnect>
|
|
<complete name="crossbar" input="carry_chain_example.I ble[3:0].out" output="ble[3:0].in">
|
|
<delay_constant max="8.044000e-11" in_port="carry_chain_example.I" out_port="ble[3:0].in" />
|
|
<delay_constant max="7.354000e-11" in_port="ble[3:0].out" out_port="ble[3:0].in" />
|
|
</complete>
|
|
<complete name="clks" input="carry_chain_example.clk" output="ble[3:0].clk">
|
|
</complete>
|
|
<direct name="clbouts" input="ble[3:0].out" output="carry_chain_example.O">
|
|
</direct>
|
|
<direct name="carry1" input="ble[0:0].cout" output="ble[1:1].cin"/>
|
|
<direct name="carry2" input="ble[1:1].cout" output="ble[2:2].cin"/>
|
|
<direct name="carry3" input="ble[2:2].cout" output="ble[3:3].cin"/>
|
|
<direct name="carry4" input="ble[3:3].cout" output="carry_chain_example.cout"/>
|
|
</interconnect>
|
|
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
|
|
|
|
<pinlocations pattern="spread"/>
|
|
<gridlocations>
|
|
<loc type="col" start="7" repeat="50" priority="7"/>
|
|
</gridlocations>
|
|
</pb_type>
|
|
|
|
<!-- This is a basic ripple-carry adder primitive
|
|
We will take care of the carry chain for it later, for now, get something that goes through the flow so that Odin II can be tested
|
|
-->
|
|
<pb_type name="adder" height="1">
|
|
<input name="a" num_pins="4"/>
|
|
<input name="b" num_pins="4"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="cout" num_pins="1"/>
|
|
<output name="sumout" num_pins="4"/>
|
|
|
|
<mode name="sample_adder">
|
|
<pb_type name="sample_adder" blif_model=".subckt adder" num_pb="1">
|
|
<input name="a" num_pins="4"/>
|
|
<input name="b" num_pins="4"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="cout" num_pins="1"/>
|
|
<output name="sumout" num_pins="4"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.a" out_port="sample_adder.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.b" out_port="sample_adder.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.cin" out_port="sample_adder.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.a" out_port="sample_adder.sumout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.b" out_port="sample_adder.sumout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_adder.cin" out_port="sample_adder.sumout"/>
|
|
</pb_type>
|
|
|
|
<interconnect>
|
|
<direct name="a2a" input="adder.a" output="sample_adder.a">
|
|
</direct>
|
|
<direct name="b2b" input="adder.b" output="sample_adder.b">
|
|
</direct>
|
|
<direct name="c2c" input="adder.cin" output="sample_adder.cin">
|
|
</direct>
|
|
<direct name="cout" input="sample_adder.cout" output="adder.cout">
|
|
</direct>
|
|
<direct name="sumout" input="sample_adder.sumout" output="adder.sumout">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
|
|
<pinlocations pattern="spread"/>
|
|
|
|
<gridlocations>
|
|
<loc type="col" start="2" repeat="13" priority="10"/>
|
|
</gridlocations>
|
|
</pb_type>
|
|
|
|
<!--
|
|
<pb_type name="sub" height="1">
|
|
<input name="a" num_pins="4"/>
|
|
<input name="b" num_pins="4"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="cout" num_pins="1"/>
|
|
<output name="sumout" num_pins="4"/>
|
|
|
|
<mode name="sample_sub">
|
|
<pb_type name="sample_sub" blif_model=".subckt sub" num_pb="1">
|
|
<input name="a" num_pins="4"/>
|
|
<input name="b" num_pins="4"/>
|
|
<input name="cin" num_pins="1"/>
|
|
<output name="cout" num_pins="1"/>
|
|
<output name="sumout" num_pins="4"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.a" out_port="sample_sub.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.b" out_port="sample_sub.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.cin" out_port="sample_sub.cout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.a" out_port="sample_sub.sumout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.b" out_port="sample_sub.sumout"/>
|
|
<delay_constant max="1.667e-9" in_port="sample_sub.cin" out_port="sample_sub.sumout"/>
|
|
</pb_type>
|
|
|
|
<interconnect>
|
|
<direct name="a2a" input="sub.a" output="sample_sub.a">
|
|
</direct>
|
|
<direct name="b2b" input="sub.b" output="sample_sub.b">
|
|
</direct>
|
|
<direct name="c2c" input="sub.cin" output="sample_sub.cin">
|
|
</direct>
|
|
<direct name="cout" input="sample_sub.cout" output="sub.cout">
|
|
</direct>
|
|
<direct name="sumout" input="sample_sub.sumout" output="sub.sumout">
|
|
</direct>
|
|
</interconnect>
|
|
</mode>
|
|
|
|
<fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
|
|
<pinlocations pattern="spread"/>
|
|
|
|
<gridlocations>
|
|
<loc type="col" start="2" repeat="13" priority="10"/>
|
|
</gridlocations>
|
|
</pb_type>
|
|
-->
|
|
|
|
</complexblocklist>
|
|
|
|
</architecture>
|