67 lines
2.7 KiB
C++
67 lines
2.7 KiB
C++
/********************************************************************
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* This file includes most utilized functions for the pb_graph_node
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* and pb_graph_pin data structure in the OpenFPGA context
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "pb_graph_utils.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function aims to find out all the pb_graph_pins that drive
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* a given pb_graph pin w.r.t. a given interconnect definition
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*******************************************************************/
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std::vector<t_pb_graph_pin*> pb_graph_pin_inputs(t_pb_graph_pin* pb_graph_pin,
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t_interconnect* selected_interconnect) {
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std::vector<t_pb_graph_pin*> inputs;
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/* Search the input edges only, stats on the size of MUX we may need (fan-in) */
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for (int iedge = 0; iedge < pb_graph_pin->num_input_edges; ++iedge) {
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/* We care the only edges in the selected mode */
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if (selected_interconnect != pb_graph_pin->input_edges[iedge]->interconnect) {
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continue;
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}
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for (int ipin = 0; ipin < pb_graph_pin->input_edges[iedge]->num_input_pins; ++ipin) {
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/* Ensure that the pin is unique in the list */
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if (inputs.end() != std::find(inputs.begin(), inputs.end(), pb_graph_pin->input_edges[iedge]->input_pins[ipin])) {
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continue;
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}
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/* Unique pin, push to the vector */
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inputs.push_back(pb_graph_pin->input_edges[iedge]->input_pins[ipin]);
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}
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}
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return inputs;
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}
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/********************************************************************
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* This function aims to find out the interconnect that drives
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* a given pb_graph pin when operating in a select mode
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*******************************************************************/
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t_interconnect* pb_graph_pin_interc(t_pb_graph_pin* pb_graph_pin,
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t_mode* selected_mode) {
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t_interconnect* interc = nullptr;
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/* Search the input edges only, stats on the size of MUX we may need (fan-in) */
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for (int iedge = 0; iedge < pb_graph_pin->num_input_edges; ++iedge) {
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/* We care the only edges in the selected mode */
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if (selected_mode != pb_graph_pin->input_edges[iedge]->interconnect->parent_mode) {
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continue;
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}
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/* There should be one unique interconnect to be found! */
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if (nullptr != interc) {
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VTR_ASSERT(interc == pb_graph_pin->input_edges[iedge]->interconnect);
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} else {
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interc = pb_graph_pin->input_edges[iedge]->interconnect;
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}
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}
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return interc;
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}
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} /* end namespace openfpga */
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