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OpenFPGA
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OpenFPGA/openfpga
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tangxifan 477c1cd062 [Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module 2021-10-01 17:38:26 -07:00
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src [Engine] Fixed a critical bug which causes undriven BL/WLs between shift register banks and child modules at the top-level module 2021-10-01 17:38:26 -07:00
CMakeLists.txt [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00