247 lines
10 KiB
C++
247 lines
10 KiB
C++
/******************************************************************************
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* This file introduces a data structure to store bitstream-related information
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*
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* General concept
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* ---------------
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* The idea is to create a unified data structure that stores all the configuration bits
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* with proper annotation to which modules in FPGA fabric it belongs to.
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* 1. It can be easily organized in fabric-dependent representation
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* (generate a sequence of bitstream which exactly fit the configuration protocol of FPGA fabric)
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* 2. Or it can be easily organized in fabric-independent representation (think about XML file)
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*
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* Cross-reference
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* ---------------
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* May be used only when you want to bind the bitstream to a specific FPGA fabric!
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* If you do so, please make sure the block name is exactly same as the instance name
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* of a child module in ModuleManager!!!
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* The configurable modules/instances in module manager are arranged
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* in the sequence to fit different configuration protocol.
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* By using the link between ModuleManager and BitstreamManager,
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* we can build a sequence of configuration bits to fit different configuration protocols.
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*
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* +------------------+ +-----------------+
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* | | block_name == instance_name | |
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* | BitstreamManager |-------------------------------->| ModuleManager |
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* | | | |
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* +------------------+ +-----------------+
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*
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* Restrictions:
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* 1. Each block inside BitstreamManager should have only 1 parent block
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* and multiple child block
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* 2. Each bit inside BitstreamManager should have only 1 parent block
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*
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******************************************************************************/
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#ifndef BITSTREAM_MANAGER_H
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#define BITSTREAM_MANAGER_H
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#include <vector>
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#include <map>
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#include <unordered_set>
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#include <unordered_map>
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#include "vtr_vector.h"
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#include "bitstream_manager_fwd.h"
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/* begin namespace openfpga */
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namespace openfpga {
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class BitstreamManager {
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public: /* Type implementations */
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/*
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* This class (forward delcared above) is a template used to represent a lazily calculated
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* iterator of the specified ID type. The key assumption made is that the ID space is
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* contiguous and can be walked by incrementing the underlying ID value. To account for
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* invalid IDs, it keeps a reference to the invalid ID set and returns ID::INVALID() for
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* ID values in the set.
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*
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* It is used to lazily create an iteration range (e.g. as returned by RRGraph::edges() RRGraph::nodes())
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* just based on the count of allocated elements (i.e. RRGraph::num_nodes_ or RRGraph::num_edges_),
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* and the set of any invalid IDs (i.e. RRGraph::invalid_node_ids_, RRGraph::invalid_edge_ids_).
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*/
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template<class ID>
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class lazy_id_iterator : public std::iterator<std::bidirectional_iterator_tag, ID> {
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public:
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//Since we pass ID as a template to std::iterator we need to use an explicit 'typename'
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//to bring the value_type and iterator names into scope
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typedef typename std::iterator<std::bidirectional_iterator_tag, ID>::value_type value_type;
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typedef typename std::iterator<std::bidirectional_iterator_tag, ID>::iterator iterator;
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lazy_id_iterator(value_type init, const std::unordered_set<ID>& invalid_ids)
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: value_(init)
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, invalid_ids_(invalid_ids) {}
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//Advance to the next ID value
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iterator operator++() {
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value_ = ID(size_t(value_) + 1);
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return *this;
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}
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//Advance to the previous ID value
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iterator operator--() {
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value_ = ID(size_t(value_) - 1);
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return *this;
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}
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//Dereference the iterator
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value_type operator*() const { return (invalid_ids_.count(value_)) ? ID::INVALID() : value_; }
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friend bool operator==(const lazy_id_iterator<ID> lhs, const lazy_id_iterator<ID> rhs) { return lhs.value_ == rhs.value_; }
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friend bool operator!=(const lazy_id_iterator<ID> lhs, const lazy_id_iterator<ID> rhs) { return !(lhs == rhs); }
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private:
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value_type value_;
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const std::unordered_set<ID>& invalid_ids_;
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};
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public: /* Public constructor */
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BitstreamManager();
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public: /* Types and ranges */
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//Lazy iterator utility forward declaration
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template<class ID>
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class lazy_id_iterator;
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typedef lazy_id_iterator<ConfigBitId> config_bit_iterator;
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typedef lazy_id_iterator<ConfigBlockId> config_block_iterator;
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typedef vtr::Range<config_bit_iterator> config_bit_range;
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typedef vtr::Range<config_block_iterator> config_block_range;
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public: /* Public aggregators */
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/* Find all the configuration bits */
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size_t num_bits() const;
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config_bit_range bits() const;
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size_t num_blocks() const;
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config_block_range blocks() const;
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public: /* Public Accessors */
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/* Find the value of bitstream */
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bool bit_value(const ConfigBitId& bit_id) const;
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/* Find the parent block of a configuration bit */
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ConfigBlockId bit_parent_block(const ConfigBitId& bit_id) const;
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/* Find a name of a block */
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std::string block_name(const ConfigBlockId& block_id) const;
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/* Find the parent of a block */
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ConfigBlockId block_parent(const ConfigBlockId& block_id) const;
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/* Find the children of a block */
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std::vector<ConfigBlockId> block_children(const ConfigBlockId& block_id) const;
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/* Find all the bits that belong to a block */
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std::vector<ConfigBitId> block_bits(const ConfigBlockId& block_id) const;
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/* Find the child block in a bitstream manager with a given name */
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ConfigBlockId find_child_block(const ConfigBlockId& block_id, const std::string& child_block_name) const;
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/* Find path id of a block */
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int block_path_id(const ConfigBlockId& block_id) const;
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/* Find input net ids of a block */
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std::string block_input_net_ids(const ConfigBlockId& block_id) const;
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/* Find input net ids of a block */
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std::string block_output_net_ids(const ConfigBlockId& block_id) const;
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public: /* Public Mutators */
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/* Add a new configuration bit to the bitstream manager */
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ConfigBitId add_bit(const ConfigBlockId& parent_block, const bool& bit_value);
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/* Reserve memory for a number of clocks */
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void reserve_blocks(const size_t& num_blocks);
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/* Reserve memory for a number of bits */
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void reserve_bits(const size_t& num_bits);
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/* Create a new block of configuration bits */
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ConfigBlockId create_block();
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/* Add a new block of configuration bits to the bitstream manager */
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ConfigBlockId add_block(const std::string& block_name);
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/* Set a name for a block */
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void set_block_name(const ConfigBlockId& block_id,
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const std::string& block_name);
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/* Reserve child blocks for a block to be memory efficient */
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void reserve_child_blocks(const ConfigBlockId& parent_block,
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const size_t& num_children);
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/* Set a block as a child block of another */
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void add_child_block(const ConfigBlockId& parent_block, const ConfigBlockId& child_block);
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/* Add a bitstream to a block */
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void add_block_bits(const ConfigBlockId& block,
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const std::vector<bool>& block_bitstream);
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/* Add a path id to a block */
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void add_path_id_to_block(const ConfigBlockId& block, const int& path_id);
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/* Add an input net id to a block */
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void add_input_net_id_to_block(const ConfigBlockId& block, const std::string& input_net_id);
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/* Add an output net id to a block */
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void add_output_net_id_to_block(const ConfigBlockId& block, const std::string& output_net_id);
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public: /* Public Validators */
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bool valid_bit_id(const ConfigBitId& bit_id) const;
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bool valid_block_id(const ConfigBlockId& block_id) const;
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bool valid_block_path_id(const ConfigBlockId& block_id) const;
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private: /* Internal data */
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/* Unique id of a block of bits in the Bitstream */
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size_t num_blocks_;
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std::unordered_set<ConfigBlockId> invalid_block_ids_;
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vtr::vector<ConfigBlockId, size_t> block_bit_id_lsbs_;
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vtr::vector<ConfigBlockId, short> block_bit_lengths_;
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/* Back-annotation for the bits */
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/* Parent block of a bit in the Bitstream
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* For each bit, the block name can be designed to be same as the instance name in a module
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* to reflect its position in the module tree (ModuleManager)
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* Note that the blocks here all unique, unlike ModuleManager where modules can be instanciated
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* Therefore, this block graph can be considered as a flattened graph of ModuleGraph
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*/
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vtr::vector<ConfigBlockId, std::string> block_names_;
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vtr::vector<ConfigBlockId, ConfigBlockId> parent_block_ids_;
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vtr::vector<ConfigBlockId, std::vector<ConfigBlockId>> child_block_ids_;
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/* The ids of the inputs of routing multiplexer blocks which is propagated to outputs
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* By default, it will be -2 (which is invalid)
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* A valid id starts from -1
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* -1 indicates an unused routing multiplexer.
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* It will be converted to a valid id by bitstream builders)
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* For used routing multiplexers, the path id will be >= 0
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*
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* Note:
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* -Bitstream manager will NOT check if the id is good for bitstream builders
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* It just store the results
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*/
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vtr::vector<ConfigBlockId, short> block_path_ids_;
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/* Net ids that are mapped to inputs and outputs of this block
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*
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* Note:
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* -Bitstream manager will NOT check if the id is good for bitstream builders
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* It just store the results
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*/
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vtr::vector<ConfigBlockId, std::string> block_input_net_ids_;
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vtr::vector<ConfigBlockId, std::string> block_output_net_ids_;
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/* Unique id of a bit in the Bitstream */
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size_t num_bits_;
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std::unordered_set<ConfigBitId> invalid_bit_ids_;
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/* value of a bit in the Bitstream */
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vtr::vector<ConfigBitId, char> bit_values_;
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vtr::vector<ConfigBitId, ConfigBlockId> bit_parent_blocks_;
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};
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} /* end namespace openfpga */
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#endif
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