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verilog_api.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_api.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_autocheck_top_testbench.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_autocheck_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_compact_netlist.c
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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verilog_compact_netlist.h
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fix a critical bug in num_reserved_sram_ports
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2019-06-05 17:31:01 -06:00 |
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verilog_decoder.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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verilog_decoder.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_formal_random_top_testbench.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_formal_random_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_formality_autodeck.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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verilog_formality_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_global.c
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_global.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_include_netlists.c
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_include_netlists.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_modelsim_autodeck.c
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_modelsim_autodeck.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_pbtypes.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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verilog_pbtypes.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_primitives.c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
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verilog_primitives.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_report_timing.c
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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verilog_report_timing.h
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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verilog_routing.c
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update gsb unique module detection and fix formal verification port direction
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2019-06-07 17:18:38 -06:00 |
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verilog_routing.h
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clean-up warnings Verilog routing generator
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2019-05-24 16:29:17 -06:00 |
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verilog_sdc.c
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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verilog_sdc.h
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Clean warnings in SDC generator and use RRSwitchBlock to replace old data structure sb_info
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2019-05-24 15:10:08 -06:00 |
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verilog_sdc_pb_types.c
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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verilog_sdc_pb_types.h
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clean up warnings in SDC pb_type generator
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2019-05-24 15:23:38 -06:00 |
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verilog_submodules.c
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
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verilog_submodules.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_tcl_utils.c
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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verilog_tcl_utils.h
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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verilog_top_netlist_utils.c
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clean up DeviceRRGSB internal data and member functions
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2019-06-07 14:45:56 -06:00 |
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verilog_top_netlist_utils.h
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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verilog_top_testbench.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_top_testbench.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_utils.c
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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verilog_utils.h
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add rr_block unique_side_module verilog generation
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2019-06-04 17:47:40 -06:00 |
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verilog_verification_top_netlist.c
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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verilog_verification_top_netlist.h
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clean warnings
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2019-05-24 16:48:08 -06:00 |
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