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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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445a24535a
OpenFPGA
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openfpga_flow
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benchmarks
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micro_benchmark
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and2_latch
History
Aram Kostanyan
b332a5a1b4
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00
..
and2_latch.act
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
and2_latch.blif
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
and2_latch.v
update microbenchmark and2 module name
2020-04-20 13:37:39 -06:00
and2_latch_verific.blif
Added 'basic_tests/verific_test' test-case.
2021-11-01 18:20:57 +05:00