374 lines
18 KiB
ReStructuredText
374 lines
18 KiB
ReStructuredText
.. _simulation_setting:
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Simulation settings
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-------------------
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For OpenFPGA using VPR7
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~~~~~~~~~~~~~~~~~~~~~~~
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All the parameters that need to be defined in the HSPICE simulations are located under a child node called <parameters>, which is under its father node <spice_settings>.
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The parameters are divided into three categories and can be defined in three XML nodes, <options>, <measure> and <stimulate>, respectively.
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* The XML node <options>
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.. code-block:: xml
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<options sim_temp=”int” post=”string”captab=”string” fast=”string”/>
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These properties define the options that will be printed in the top SPICE netlists.
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* **sim_temp:** specify the temperature which will be defined in SPICE netlists. In the top SPICE netlists, it will show as .temp <int>.
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* **post:** [on|off]. Specify if the simulation waveforms should be printed out after SPICE simulations. In all the SPICE netlists, it will show as .option POST when turned on.
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.. note:: when the SPICE netlists are large or a long simulation duration is defined, the post option is recommended to be off. If not, huge disk space will be occupied by the waveform files.
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* **captab:** [on|off]. Specify if the capacitances of all the nodes in the SPICE netlists will be printed out. In the top SPICE netlists, it will show as .option CAPTAB when turned on. When turned on, the SPICE simulation runtime may increase.
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* The XML node <stimulate>
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.. code-block:: xml
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<stimulate>
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<clock op_freq=”auto|float” sim_slack=”float” prog_freq=”float”>
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<rise slew_time=”float” slew_type=”string”/>
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<fall slew_time=”float” slew_type=”string”/>
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</clock>
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</stimulate>
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Define stimulates for the clock signal.
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* **op_freq:** either auto or a float number (unit:[Hz]) Specify the operation clock frequency that is used in SPICE simulations. This frequency is used in testbenches for operation phase simulation. Note that this is a mandatory option. Users have to specify either this frequency is automatically determined by assigning “auto” or give an exact number. If this clock frequency is specified, the sim_slack option is disregarded.
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* **sim_slack:** add slack to the critical path delay in the SPICE simulation. For example, sim_slack=0.2 implies that the clock period in SPICE simulations is 1.2 of the critical path delay reported by VPR. **Only valid when option op_freq is not specified.**
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* **prog_freq:** Specify the programming clock frequency that is used in SPICE simulations. This frequency is used in testbenches for programming phase simulation.
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* **slew_type & slew_time:** define the slew of clock signals at the rising/falling edge. Property slew_type can be either absolute or fractional [abs|frac].
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* The type of **absolute** implies that the slew time is the absolute value. For example, slew_time=20e-12, slew_type=abs means that the slew of a clock signal is 20ps.
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* The type of **fractional** means that the slew time is related to the period (frequency) of the clock signal. For example, slew_time=0.05, slew_type=frac means that the slew of a clock signal takes 5% of the period of the clock.
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:numref:`fig_meas_edge` depicts the definition of the slew and delays of signals and the parameters that can be supported by FPGA-SPICE.
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.. code-block:: xml
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<stimulate>
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<input>
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<rise slew_time=”float” slew_type=”string”/>
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<fall slew_time=”float” slew_type=”string”/>
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</input>
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</stimulate>
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Define the slew of input signals at the rising/falling edge.
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* **slew_type & slew_time:** define the slew of all the input signals at the rising/falling edge. Property slew_type can be either absolute or fractional [abs|frac].
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* The type of **absolute** implies that the slew time is the absolute value. For example, slew_time=20e-12, slew_type=abs means that the slew of a clock signal is 20ps.
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* The type of **fractional** means that the slew time is related to the period (frequency) of the clock signal. For example, slew_time=0.05, slew_type=frac means that the slew of a clock signal takes 5% of the period of the clock.
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.. note:: These slew settings are valid for all the input signals of the testbenches in different complexity levels.
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.. _fig_meas_edge:
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.. figure:: figures/meas_edge.png
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:scale: 100%
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:alt: map to buried traesure
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Parameters in measuring the slew and delay of signals
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* The XML node <measure>
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.. code-block:: xml
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<measure sim_num_clock_cycle=”int”accuracy=”float”accuracy_type=”string”/>
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* **sim_num_clock_cycle:** can be either “auto” or an integer. By setting to “auto”, FPGA-SPICE automatically determines the number of clock cycles to simulate, which is related to the average of all the signal density in ACE2 results. When set to an integer, FPGA-SPICE will use the given number of clock cycles in the SPICE netlists.
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* **accuracy_type:** [abs|frac]. Specify the type of transient step in SPICE simulation.
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* When **abs** is selected, the accuracy should be the absolute value, such as 1e-12.
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* When **frac** is selected, the accuracy is the number of simulation points in a clock cycle period, for example, 100.
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* **accuracy:** specify the transient step in SPICE simulation. Typically, the smaller the step is, the higher the accuracy that can be reached while the long simulation runtime is. The recommended accuracy is between 0.1ps and 0.01ps, which generates good accuracy and runtime is not significantly long.
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.. note:: Users can define the parameters in measuring the slew of signals, under a child node <slew> of the node <measure>.
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.. code-block:: xml
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<rise upper_thres_pct=”float” lower_thres_pct=”float”/>
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Define the starting and ending point in measuring the slew of a rising edge of a signal.
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* **upper_thres_pct:** the ending point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of upper_thres_pct=0.95 is depicted in Figure 2.
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* **lower_thres_pct:** the starting point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of lower_thres_pct=0.05 is depicted in Figure 2.
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.. code-block:: xml
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<fall upper_thres_pct=”float” lower_thres_pct=”float”/>
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* **upper_thres_pct:** the ending point in measuring the slew of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of upper_thres_pct=0.05 is depicted in Figure 2.
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* **lower_thres_pct:** the starting point in measuring the slew of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of lower_thres_pct=0.95 is depicted in Figure 2.
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.. note:: Users can define the parameters related to measurements of delays between signals, under a child node <delay> of the node <measure>.
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.. code-block:: xml
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<rise input_thres_pct=”float” output_thres_pct=”float”/>
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Define the starting and ending point in measuring the delay between two signals when they are both at a rising edge.
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* **input_thres_pct:** the starting point in measuring the delay of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of input_thres_pct=0.5 is depicted in Figure 2.
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* **output_thres_pct:** the ending point in measuring the delay of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of output_thres_pct=0.5 is depicted in Figure 2.
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.. code-block:: xml
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<fall input_thres_pct=”float” output_thres_pct=”float”/>
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Define the starting and ending point in measuring the delay between two signals when they are both at a falling edge.
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* **input_thres_pct:** the starting point in measuring the delay of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, upper_thres_pct=0.5 is depicted in :numref:`fig_meas_edge`.
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* **output_thres_pct:** the ending point in measuring the delay of a falling edge. It is expressed as a percentage of the maximum voltage of a signal. For example, lower_thres_pct=0. 5 is depicted in :numref:`fig_meas_edge`.
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For OpenFPGA using VPR8
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~~~~~~~~~~~~~~~~~~~~~~~
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All the simulation settings are stored under the XML node ``<openfpga_simulation_setting>``
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General organization is as follows
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.. code-block:: xml
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<openfpga_simulation_setting>
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<clock_setting>
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<operating frequency="<int>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
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<programming frequency="<int>"/>
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</clock_setting>
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<simulator_option>
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<operating_condition temperature="<int>"/>
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<output_log verbose="<bool>" captab="<bool>"/>
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<accuracy type="<string>" value="<float>"/>
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<runtime fast_simulation="<bool>"/>
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</simulator_option>
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<monte_carlo num_simulation_points="<int>"/>
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<measurement_setting>
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<slew>
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<rise upper_thres_pct="<float>" lower_thres_pct="<float>"/>
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<fall upper_thres_pct="<float>" lower_thres_pct="<float>"/>
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</slew>
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<delay>
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<rise input_thres_pct="<float>" output_thres_pct="<float>"/>
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<fall input_thres_pct="<float>" output_thres_pct="<float>"/>
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</delay>
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</measurement_setting>
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<stimulus>
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<clock>
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<rise slew_type="<string>" slew_time="<float>"/>
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<fall slew_type="<string>" slew_time="<float>"/>
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</clock>
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<input>
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<rise slew_type="<string>" slew_time="<float>"/>
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<fall slew_type="<string>" slew_time="<float>"/>
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</input>
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</stimulus>
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</openfpga_simulation_setting>
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Clock Setting
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^^^^^^^^^^^^^
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Clock setting focuses on defining the clock periods to applied on FPGA fabrics
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As a programmable device, an FPGA has two types of clocks.
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The first is the operating clock, which is applied by users' implementations.
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The second is the programming clock, which is applied on the configuration protocol to load users' implementation to FPGA fabric.
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OpenFPGA allows users to freely define these clocks as well as the number of clock cycles.
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We should the full syntax in the code block below and then provide details on each of them.
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.. code-block:: xml
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<clock_setting>
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<operating frequency="<float>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
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<programming frequency="<float>"/>
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</clock_setting>
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Operating clock setting
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```````````````````````
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Operating clocks are defined under the XML node ``<operating>``
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.. option:: <operating frequency="<float>|<string>" num_cycles="<int>|<string>" slack="<float>"/>
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- ``frequency="<float|string>``
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Specify frequency of the operating clock. OpenFPGA allows users to specify an absolute value in the unit of ``[Hz]``
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Alternatively, users can bind the frequency to the maximum clock frequency analyzed by VPR STA engine.
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This is very useful to validate the maximum operating frequency for users' implementations
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In such case, the value of this attribute should be a reserved word ``auto``.
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- ``num_cycles="<int>|<string>"``
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can be either ``auto`` or an integer. When set to ``auto``, OpenFPGA will infer the number of clock cycles from the average/median of all the signal activities.
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When set to an integer, OpenFPGA will use the given number of clock cycles in HDL and SPICE simulations.
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- ``slack="<float>"``
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add a margin to the critical path delay in the HDL and SPICE simulations.
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This parameter is applied to the critical path delay provided by VPR STA engine.
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So it is only valid when option ``frequency`` is set to ``auto``.
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This aims to compensate any inaccuracy in STA results.
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Typically, the slack value is between ``0`` and ``1``.
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For example, ``slack=0.2`` implies that the actual clock period in simulations is 120% of the critical path delay reported by VPR.
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.. note:: Only valid when option ``frequency`` is set to ``auto``
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.. warning:: Avoid to use a negative slack! This may cause your simulation to fail!
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Programming clock setting
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`````````````````````````
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Programming clocks are defined under the XML node ``<programming>``
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.. option:: <programming frequency="<float>"/>
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- ``frequency="<float>"``
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Specify the frequency of the programming clock using an absolute value in the unit of ``[Hz]``
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This frequency is used in testbenches for programming phase simulation.
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.. note:: Programming clock frequency is typically much slower than the operating clock and strongly depends on the process technology. Suggest to characterize the speed of your configuration protocols before specifying a value!
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Simulator Option
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^^^^^^^^^^^^^^^^
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This XML node includes universal options available in both HDL and SPICE simulators.
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.. note:: This is mainly used by FPGA-SPICE
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Operating condition
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```````````````````
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.. option:: <operating_condition temperature="<int>"/>``
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- ``temperature="<int>"``
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Specify the temperature which will be defined in SPICE netlists. In the top SPICE netlists, it will show as
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.. code-block:: python
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.temp <int>
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Output logs
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```````````
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.. option:: <output_log verbose="<bool>" captab="<bool>"/>``
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Specify the options in outputting simulation results to log files
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- ``verbose="true|false"``
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Specify if the simulation waveforms should be printed out after SPICE simulations. If turned on, it will show in all the SPICE netlists
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.. code-block:: python
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.option POST
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.. note:: when the SPICE netlists are large or a long simulation duration is defined, the post option is recommended to be off. If not, huge disk space will be occupied by the waveform files.
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- ``captab="true|false"``
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Specify if the capacitances of all the nodes in the SPICE netlists will be printed out. If turned on, it will show in the top-level SPICE netlists
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.. code-block:: python
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.option CAPTAB
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.. note:: When turned on, the SPICE simulation runtime may increase.
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Simulation Accuracy
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```````````````````
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.. option:: <accuracy type="<string>" value="<float>"/>``
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Specify the simulation steps (accuracy) to be used
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- ``type="abs|frac"``
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Specify the type of transient step in SPICE simulation.
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* When ``abs`` is selected, the accuracy should be the absolute value, such as ``1e-12``.
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* When ``frac`` is selected, the accuracy is the number of simulation points in a clock cycle period, for example, 100.
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- ``value="<float>"``
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Specify the transient step in SPICE simulation. Typically, the smaller the step is, the higher the accuracy that can be reached while the long simulation runtime is. The recommended accuracy is between 0.1ps and 0.01ps, which generates good accuracy and runtime is not significantly long.
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Simulation Speed
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````````````````
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.. option:: <runtime fast_simulation="<bool>"/>
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Specify if any runtime optimization will be applied to the simulator.
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- ``fast_simulation="true|false"``
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Specify if fast simulation is turned on for the simulator.
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If turned on, it will show in the top-level SPICE netlists
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.. code-block:: python
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.option fast
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Monte Carlo Simulation
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``````````````````````
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.. option:: <monte_carlo num_simulation_points="<int>"/>
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Run SPICE simulations in monte carlo mode.
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This is mainly for FPGA-SPICE
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When turned on, FPGA-SPICE will apply the device variation defined in :ref:`technology_library` to monte carlo simulation
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- ``num_simulation_points="<int>"``
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Specify the number of simulation points to be considered in monte carlo.
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The larger the number is, the longer simulation time will be but more accurate the results will be.
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Measurement Setting
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```````````````````
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- Users can define the parameters in measuring the slew of signals, under XML node ``<slew>``
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- Users can define the parameters in measuring the delay of signals, under XML node ``<delay>``
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Both delay and slew measurement share the same syntax in defining the upper and lower voltage thresholds.
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.. option:: <rise|fall upper_thres_pct="<float>" lower_thres_pct="<float>"/>
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Define the starting and ending point in measuring the slew of a rising or a falling edge of a signal.
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- ``upper_thres_pct="<float>"`` the ending point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of upper_thres_pct=0.95 is depicted in :numref:`fig_measure_edge`.
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- ``lower_thres_pct="<float>"`` the starting point in measuring the slew of a rising edge. It is expressed as a percentage of the maximum voltage of a signal. For example, the meaning of lower_thres_pct=0.05 is depicted in :numref:`fig_measure_edge`.
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.. _fig_measure_edge:
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.. figure:: figures/meas_edge.png
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:scale: 80%
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:alt: map to buried traesure
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An illustrative example on measuring the slew and delay of signals
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Stimulus Setting
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````````````````
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Users can define the slew time of input and clock signals to be applied to FPGA I/Os in testbenches under XML node ``<clock>`` and ``<input>`` respectively.
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This is used by FPGA-SPICE in generating testbenches
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.. option:: <rise|fall slew_type="<string>" slew_time="<float>"/>
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Specify the slew rate of an input or clock signal at rising or falling edge
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- ``slew_type="[abs|frac]"`` specify the type of slew time definition at the rising or falling edge of a lock/input port.
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* The type of ``abs`` implies that the slew time is the absolute value. For example, ``slew_type="abs" slew_time="20e-12"`` means that the slew of a clock signal is 20ps.
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* The type of ``frac`` means that the slew time is related to the period (frequency) of the clock signal. For example, ``slew_type="frac" slew_time="0.05"`` means that the slew of a clock signal takes 5% of the period of the clock.
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- ``slew_time="<float>"`` specify the slew rate of an input or clock signal at the rising/falling edge.
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:numref:`fig_measure_edge` depicts the definition of the slew and delays of signals and the parameters that can be supported by FPGA-SPICE.
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