tangxifan 185e574738 removed redundant include files in all the verilog netlists except the top one		2020-04-24 20:21:32 -06:00
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src	removed redundant include files in all the verilog netlists except the top one	2020-04-24 20:21:32 -06:00
test_blif	add missing files for micro benchmarks	2020-03-20 11:08:55 -06:00
test_openfpga_arch	now inout must be global port and I/O port so that it will appear in the top-level module	2020-04-08 16:54:08 -06:00
test_script	add fabric bitstream writer	2020-04-21 12:02:10 -06:00
test_vpr_arch	add arch file with spy pads	2020-04-22 12:56:09 -06:00
CMakeLists.txt	add simulation ini file writer	2020-02-27 18:01:47 -07:00